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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Chern; Horng-Nan
Address:
Tainan Hsien, TW
No. of patents:
10
Patents:












Patent Number Title Of Patent Date Issued
6429135 Method of reducing stress between a nitride silicon spacer and a substrate August 6, 2002
The semiconductor wafer includes a substrate, a gate positioned on the substrate, a cap layer positioned on top of the gate, and a silicon oxide spacer positioned around both the gate and the cap layer. Firstly, a dielectric layer is formed on the semiconductor wafer to cover the gate.
6403411 Method for manufacturing lower electrode of DRAM capacitor June 11, 2002
A method for manufacturing the lower electrode of a DRAM capacitor. The method includes depositing polysilicon instead of amorphous silicon to form the lower electrode. Because polysilicon has a higher depositing temperature, it has a higher depositing rate capable of shortening depo
6303435 Method of fabricating a wide-based box-structured capacitor containing hemi-spherical grains October 16, 2001
A method of fabricating a wide-based boxed-structured capacitor containing hemi-spherical silicon grains. A substrate is provided with a source/drain and a first dielectric layer is formed on the substrate with a node contact opening. Then a doped polysilicon layer and a doped amorphous
6255229 Method for forming semiconductor dielectric layer July 3, 2001
A method for forming a semiconductor dielectric layer comprising the steps of providing a substrate having a plurality of semiconductor devices already formed thereon, and then forming a first dielectric layer over the substrate. Next, a silicon oxy-nitride layer is formed over the first
6238974 Method of forming DRAM capacitors with a native oxide etch-stop May 29, 2001
A process of fabricating a bottom electrode for the storage capacitors of DRAM is disclosed. The process includes first forming an insulation layer on the surface of the device substrate, with the insulation layer patterned to form a contact opening that exposes a source/drain region of
6211021 Method for forming a borderless contact April 3, 2001
A method of forming a borderless contact is described. An ion implantation process and a thermal process are performed on a device isolation structure to form a silicon nitride layer therein. During a process of forming a borderless contact window, the silicon nitride layer can serve
6140202 Method of fabricating double-cylinder capacitor October 31, 2000
A method for fabricating a double-cylinder capacitor is provided. The double-cylinder capacitor has a storage electrode having dual, concentric cylinder structures. The dielectric layer and the top electrode are formed in sequence over the bottom electrode. The storage area is thus enlar
6124161 Method for fabricating a hemispherical silicon grain layer September 26, 2000
A method for forming a hemispherical silicon grain (HSG) layer on a polysilicon electrode is provided. The method is suitable for a substrate, which has a dielectric layer over the substrate with an opening to expose the substrate, and a polysilicon layer is formed over the substrate. A
6100158 Method of manufacturing an alignment mark with an etched back dielectric layer and a transparent August 8, 2000
A method of manufacturing an alignment mark. A substrate having a device region and an alignment mark region is provided. The device region is higher than the alignment mark region. The device region comprises an active region. An isolation structure is formed in the substrate at the
6063660 Fabricating method of stacked type capacitor May 16, 2000
A fabricating method and a structure of a stacked-type capacitor is provided comprising forming a first dielectric layer having a first via on a semiconductor substrate. A first conductive layer is filled into the first via. Then, insulating layers and dielectric layers are formed. A










 
 
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