| Patent Number |
Title Of Patent |
Date Issued |
| 8158481 |
CMOS structure and method for fabrication thereof using multiple crystallographic orientations a |
April 17, 2012 |
| Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A |
| 8138574 |
PCM with poly-emitter BJT access devices |
March 20, 2012 |
| A phase change memory (PCM) includes an array comprising a plurality of memory cells, a memory cell comprising a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semic |
| 7847356 |
Metal gate high-K devices having a layer comprised of amorphous silicon |
December 7, 2010 |
| Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active |
| 7833849 |
Method of fabricating a semiconductor structure including one device region having a metal gate |
November 16, 2010 |
| A method of fabricating semiconductor structure is provided in which at least one nFET device and a least one pFET device are formed on a semiconductor substrate. Each device region formed includes a dielectric stack that has a net dielectric constant equal to or greater than silicon |
| 7790592 |
Method to fabricate metal gate high-k devices |
September 7, 2010 |
| Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active |
| 7671421 |
CMOS structure and method for fabrication thereof using multiple crystallographic orientations a |
March 2, 2010 |
| Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A |
| 7598097 |
Method of fabricating a magnetic shift register |
October 6, 2009 |
| A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. A trench is etched in the multi-layer stack structure. A selective etching process is used to corrugate the walls of |
| 7498235 |
Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates |
March 3, 2009 |
| A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a |
| 7435652 |
Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOS |
October 14, 2008 |
| Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the com |
| 7416905 |
Method of fabricating a magnetic shift register |
August 26, 2008 |
| A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. A trench is etched in the multi-layer stack structure. A selective etching process is used to corrugate the walls of |
| 7315065 |
Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates |
January 1, 2008 |
| A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a |
| 7138319 |
Deep trench isolation of embedded DRAM for improved latch-up immunity |
November 21, 2006 |
| A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of |
| 7108797 |
Method of fabricating a shiftable magnetic shift register |
September 19, 2006 |
| A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. Vias of approximately 10 microns tall with a cross-section on the order of 100 nm.times.100 nm are etched in this m |
| 7084460 |
Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates |
August 1, 2006 |
| A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a |
| 6955926 |
Method of fabricating data tracks for use in a magnetic shift register memory device |
October 18, 2005 |
| A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. Vias of approximately 10 microns tall with a cross-section on the order of 100 nm.times.100 nm are etched in this m |
| 6914320 |
Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof |
July 5, 2005 |
| An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and |
| 6887783 |
Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof |
May 3, 2005 |
| An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and |
| 6885080 |
Deep trench isolation of embedded DRAM for improved latch-up immunity |
April 26, 2005 |
| A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the |
| 6878611 |
Patterned strained silicon for high performance circuits |
April 12, 2005 |
| In the preferred embodiment of this invention a method is described to convert patterned SOI regions into patterned SGOI (silicon-germanium on oxide) by the SiGe/SOI thermal mixing process to further enhance performance of the logic circuit in an embedded DRAM. The SGOI region acts a |
| 6812114 |
Patterned SOI by formation and annihilation of buried oxide regions during processing |
November 2, 2004 |
| A method of fabricating a silicon-on-insulator (SOI) substrate including an ultra-thin top Si-containing layer and at least one patterned buried semi-insulating or insulating region having well defined edges is provided. The method includes a step of implanting first ions into a surf |
| 6657261 |
Ground-plane device with back oxide topography |
December 2, 2003 |
| A ground-plane SOI device including at least a gate region that is formed on a top Si-containing layer of a SOI wafer, said top Si-containing layer being formed on a non-planar buried oxide layer, wherein said non-planar buried oxide layer has a thickness beneath the gate region that is |
| 6635517 |
Use of disposable spacer to introduce gettering in SOI layer |
October 21, 2003 |
| A method of forming a self-aligned gettering region within an SOI substrate is provided. Specifically, the inventive method includes the steps of forming a disposable spacer on each vertical sidewall of a patterned gate stack region, the patterned gate stack region being formed on a top |
| 6593205 |
Patterned SOI by formation and annihilation of buried oxide regions during processing |
July 15, 2003 |
| A method of fabricating a silicon-on-insulator (SOI) substrate including at least one patterned buried oxide region having well defined edges is provided. The method includes a step of implanting first ions into a surface of a Si-containing substrate so as to form an implant region of |
| 6566177 |
Silicon-on-insulator vertical array device trench capacitor DRAM |
May 20, 2003 |
| A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silic |
| 6521949 |
SOI transistor with polysilicon seed |
February 18, 2003 |
| Short channel effects are effectively suppressed by steep impurity concentration gradients which can be placed with improved accuracy of location and geometry while relaxing process tolerances by implanting impurities in a polysilicon seed adjacent a conduction channel of a transisto |
| 6432754 |
Double SOI device with recess etch and epitaxy |
August 13, 2002 |
| The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in |
| 6426252 |
Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap |
July 30, 2002 |
| A silicon on insulator (SOI) dynamic random access memory (DRAM) cell, array and method of manufacture. The memory cell includes a vertical access transistor above a trench storage capacitor in a layered wafer. A buried oxide (BOX) layer formed in a silicon wafer isolates an SOI layer |
| 6319794 |
Structure and method for producing low leakage isolation devices |
November 20, 2001 |
| A shallow trench isolation structure for a semiconductor device and the method for manufacturing the shallow trench isolation device within a semiconductor substrate. The shallow trench isolation structure is divot-free and includes un-annealed dielectric material as the trench fill |
| 6271578 |
Crack stops |
August 7, 2001 |
| Crack stops for substantially preventing cracks and chips produced along the dicing channel from spreading into the active areas of the ICs are described. The crack stops are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the chip |
| 6194736 |
Quantum conductive recrystallization barrier layers |
February 27, 2001 |
| Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of quantum conductive recrystallization barrier layers. The quantum conductive layers are preferably used in trench capacitors to act as recrystallization barrier |
| 6084287 |
Crack stops |
July 4, 2000 |
| Crack stops for substantially preventing cracks and chips produced along the dicing channel from spreading into the active areas of the ICs are described. The crack stops are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the chip |
| 6025639 |
Crack stops |
February 15, 2000 |
| Crack stops for substantially preventing cracks and chips produced along the dicing channel from spreading into the active areas of the ICs are described. The crack stops are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the chip |
| 5789302 |
Crack stops |
August 4, 1998 |
| Crack stops for substantially preventing cracks and chips produced along the dicing channel from spreading into the active areas of the ICs are described. The crack stops are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the chip |
| 5266505 |
Image reversal process for self-aligned implants in planar epitaxial-base bipolar transistors |
November 30, 1993 |
| An image reversal process for self-aligned implants in which a mask opening and plug in the opening are used to enable one implant in the mask opening, another self-aligned implant in the region surrounding the opening, and a self-aligned electrode to be formed in the opening. |
| 5185276 |
Method for improving low temperature current gain of bipolar transistors |
February 9, 1993 |
| A method for improving the low temperature current gain of silicon bipolar transistors by implanting a first and a second impurity of the same conductivity type into the base region to provide a high doping level base that increases bandgap narrowing without decreasing freeze-out activat |
| 5117271 |
Low capacitance bipolar junction transistor and fabrication process therfor |
May 26, 1992 |
| This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignmen |
| 5106767 |
Process for fabricating low capacitance bipolar junction transistor |
April 21, 1992 |
| This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignmen |
| 5017990 |
Raised base bipolar transistor structure and its method of fabrication |
May 21, 1991 |
| The invention relates to a bipolar transistor structure which includes a layer of semiconductor material having a single crystal raised base, a single crystal or polycrystalline emitter and adjacent polycrystalline regions which provide an electrical connection to the emitter. The in |
