| Patent Number |
Title Of Patent |
Date Issued |
| 7555631 |
RISC microprocessor architecture implementing multiple typed register sets |
June 30, 2009 |
| A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set |
| 7409097 |
Video encoding using variable bit rates |
August 5, 2008 |
| A system and method is provided for variable bit rate encoding using a complexity ratio. Quantization parameter is calculated using a complexity ratio, which is equal to a local complexity divided by a global complexity. Complex pictures are allocated a larger bit budget relative to |
| 6934332 |
Motion estimation using predetermined pixel patterns and subpatterns |
August 23, 2005 |
| A method and system is provided for calculating motion vectors of macroblocks in a digital image of a digital video stream. The method and system reduces the computational overhead of calculating motion vectors computing difference measures using a predetermined pattern of pixels in |
| 6891890 |
Multi-phase motion estimation system and method |
May 10, 2005 |
| A method and system is provided for calculating motion vectors of macroblocks in a digital image of a digital video stream. The method and system reduces the computational overhead of calculating motion vectors computing difference measures using a multi-phase computational scheme. S |
| 6813315 |
Motion estimation using multiple search windows |
November 2, 2004 |
| A method and system is provided for calculating motion vectors of macroblocks in a digital image of a digital video stream. The method and system reduces the computational overhead of calculating motion vectors by limiting the search for the origin block to a coarse search window and a |
| 6249856 |
RISC microprocessor architecture implementing multiple typed register sets |
June 19, 2001 |
| A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set |
| 6044449 |
RISC microprocessor architecture implementing multiple typed register sets |
March 28, 2000 |
| A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set |
| 5838986 |
RISC microprocessor architecture implementing multiple typed register sets |
November 17, 1998 |
| A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set |
| 5731850 |
Hybrid hierarchial/full-search MPEG encoder motion estimation |
March 24, 1998 |
| An apparatus and method for determining inter-frame motion during compression of digital video data incorporates a computationally efficient hierarchical block-matching motion estimation technique in conjunction with a full-search block-matching approach. In the hierarchical block-ma |
| 5682546 |
RISC microprocessor architecture implementing multiple typed register sets |
October 28, 1997 |
| A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set |
