| Patent Number |
Title Of Patent |
Date Issued |
| 7554509 |
Column antenna apparatus and method for manufacturing the same |
June 30, 2009 |
| A column antenna apparatus and a manufacturing method thereof are disclosed. This invention forms a metal layer with at least two spiral structures on a column body. The column antenna apparatus can simplify the manufacturing process and enhance the yield rate. The column antenna app |
| 7466268 |
Frequency adjustable antenna apparatus and a manufacturing method thereof |
December 16, 2008 |
| A frequency adjustable antenna apparatus and a manufacturing method thereof are disclosed. The antenna apparatus includes a plurality of antenna paths and the length of the antenna path is changed via the soldering pads. Therefore, the receiving frequency of the antenna can be change |
| 7414592 |
Antenna apparatus |
August 19, 2008 |
| An antenna apparatus includes a hollow column, a conductive cable, a first metal wire, a column structure, and a second metal wire. The conductive cable is received in the hollow column, and the conductive cable electrically contacts the hollow column via a second conductive wire lay |
| 7342554 |
Column antenna apparatus and a manufacturing method thereof |
March 11, 2008 |
| A column antenna apparatus and a manufacturing method thereof are disclosed. This invention forms a spiral metal layer on a column body. The column antenna apparatus can simplify the manufacturing process and enhance the yield rate. The column antenna apparatus includes a column body |
| 7256742 |
Flexible antenna apparatus and a manufacturing method thereof |
August 14, 2007 |
| A flexible antenna apparatus and a manufacturing method thereof are provided for wireless communication devices. The flexible antenna has a metal layer with an adhesive layer pasted onto the back surface of the metal layer, so that it can be directly pasted onto the housing of the wi |
| 6855599 |
Fabrication method of a flash memory device |
February 15, 2005 |
| A flash memory device includes a substrate having a trench, a deep N-type well region in the substrate, a stacked gate structure on the substrate, a first and a second spacer on a sidewall of the stacked gate, wherein the first spacer is connected with the top of the trench, a source reg |
| 6730959 |
Structure of flash memory device and fabrication method thereof |
May 4, 2004 |
| A flash memory device includes a substrate having a trench, a deep N-type well region in the substrate, a stacked gate structure on the substrate, a first and a second spacer on a sidewall of the stacked gate, wherein the first spacer is connected with the top of the trench, a source reg |
| 6706602 |
Manufacturing method of flash memory |
March 16, 2004 |
| A manufacturing method of flash memory. A substrate is provided, on which a gate structure is formed. A first spacer is formed on the sidewalls of the gate structure. A source region is formed in the substrate at one side of the gate structure. A first conductive layer and a sacrificial |
| 6628550 |
Structure, fabrication and operation method of flash memory device |
September 30, 2003 |
| A structure of a flash memory device. The flash memory comprises a deep n-well formed in a substrate, a p-well in the deep n-well, a stacked gate structure on the substrate, source and drain regions in the substrate at two respective sides of the stacked gate, an n-well extending from th |
| 6281089 |
Method for fabricating an embedded flash memory cell |
August 28, 2001 |
| A method for embedded flash cell fabrication beyond 0.35 .XI.m generation. First, a relatively thick field oxide layer is formed on the P-type substrate to separate the flash cell areas and logic cell area. The flash cell areas are divided into tunnel oxide window and capacitor coupling |
| 6261906 |
Method for forming a flash memory cell with improved drain erase performance |
July 17, 2001 |
| The method for forming a flash memory cell mainly includes the steps as follows. At first, a semiconductor substrate having isolation regions thereon and having a well region provided between the isolation regions is provided. A tunnel oxide layer is formed on the well region and a first |
| 6232180 |
Split gate flash memory cell |
May 15, 2001 |
| A split gate flash memory cell formed in a semiconductor substrate is disclosed. The memory cell comprises: a deep n-well formed in the substrate; a p-well formed in the deep n-well; a select gate structure formed on the p-well, the select gate structure comprising a stack of a gate |
| 6111788 |
Method for programming and erasing a triple-poly split-gate flash |
August 29, 2000 |
| A method of programming and erasing a triple-poly split-gate flash memory. The memory cell is programmed by substrate hot-electron injection and erased by the tunneling effect and an inversion layer near the drain region. Such programming/erasing procedures can achieve uniform injection |
| 6111286 |
Low voltage low power n-channel flash memory cell using gate induced drain leakage current |
August 29, 2000 |
| A flash memory cell formed on a semiconductor substrate is disclosed. The cell comprises: a p-well formed in the substrate; a gate structure formed atop the p-well, the gate structure including a control gate and a floating gate, the floating gate electrically isolated from the control |
| 6110790 |
Method for making a MOSFET with self-aligned source and drain contacts including forming an oxid |
August 29, 2000 |
| A method for making a MOSFET in a semiconductor substrate with self aligned source and drain contacts. The method comprises forming a gate oxide layer on the substrate followed by forming a polysilicon gate on the gate oxide layer. A liner oxide layer is formed on the gate and the gate o |
| 6091635 |
Electron injection method for substrate-hot-electron program and erase V.sub.T tightening for ET |
July 18, 2000 |
| A new method for injecting electrons from a forward biased deep n-well to p-well junction underneath the channel area of a triple-well ETOX cell during substrate hot electron (SHE) programming. The ETOX cell has a control gate, a floating gate, a deep n-well formed in the substrate, a |
| 6087695 |
Source side injection flash EEPROM memory cell with dielectric pillar and operation |
July 11, 2000 |
| A semiconductor flash memory cell. A p-well is formed in a semiconductor substrate. A thin oxide layer is formed over the p-well and semiconductor substrate. A dielectric pillar extending up from the semiconductor substrate is formed to support a control gate. A select gate is formed |
| 6066875 |
Method of fabricating split-gate source side injection flash EEPROM array |
May 23, 2000 |
| A split-gate source side injection flash EEPROM array structure and method of fabrication that utilizes the same polysilicon layer to form the control gate and the floating gate. Furthermore, there is a tunneling oxide layer underneath the floating gate, a gate oxide layer underneath |
| 6026028 |
Hot carrier injection programming and negative gate voltage channel erase flash EEPROM structure |
February 15, 2000 |
| A flash electrical erasable programmable read only memory structure that utilizes hot carrier injection for programming and negative gate voltage to carry out channel erase operations. Characteristic of the memory structure includes a triple well structure having a P-well and an N-well |
| 5998262 |
Method for manufacturing ETOX cell having damage-free source region |
December 7, 1999 |
| A method for manufacturing EPROM tunnel oxide cell having a damage-free source region. The method comprises the step of providing a substrate having a device region formed thereon, and then forming an ion-implanted region in the device area. Next, a gate oxide layer is formed over the |
| 5918121 |
Method of reducing substrate losses in inductor |
June 29, 1999 |
| A method for making planar silicon-based inductor structure with improved Q is disclosed. This method includes the steps of: (a) providing a lightly-doped P-type substrate as a starting wafer; (b) forming a preliminary oxide layer on the lightly-doped P-type substrate; (c) forming a |
