| Patent Number |
Title Of Patent |
Date Issued |
| 6674135 |
Semiconductor structure having elevated salicided source/drain regions and metal gate electrode |
January 6, 2004 |
| A semiconductor structure an a process for its manufacture. First and second gate dielectric layers are formed on a semiconductor substrate between nitride spacers, and a metal gate electrode is formed on the gate dielectric layers. Lightly-doped drain regions and source/drain regions |
| 6638829 |
Semiconductor structure having a metal gate electrode and elevated salicided source/drain region |
October 28, 2003 |
| A semiconductor structure and a process for its manufacture. A metal gate electrode is formed on a semiconductor substrate, the gate electrode being between nitride spacers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode |
| 6417539 |
High density memory cell assembly and methods |
July 9, 2002 |
| A memory cell assembly includes a substrate, a first electrode, and a second electrode layer. The first electrode is disposed over the substrate and the second electrode layer is disposed over the first electrode. The second electrode layer includes two or more second electrodes. Dielect |
| 6300205 |
Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo |
October 9, 2001 |
| One method of making a semiconductor device includes forming a gate electrode on a substrate and forming a spacer on a sidewall of the gate electrode. An active region is then formed in the substrate and adjacent to the spacer, but spaced apart from the gate electrode, using a first |
| 6242330 |
Process for breaking silicide stringers extending between silicide areas of different active reg |
June 5, 2001 |
| A process for breaking silicide stringers extending between silicide regions of different active regions on a semiconductor device is provided. Consistent with an exemplary fabrication process, two adjacent silicon active regions are formed on a substrate and a metal layer is formed over |
| 6162694 |
Method of forming a metal gate electrode using replaced polysilicon structure |
December 19, 2000 |
| A metal gate electrode formed with high temperature activation of source/drain and LDD implants and a process for manufacture. A polysilicon alignment structure is formed on a silicon substrate. Source/drain regions are formed in alignment with the polysilicon alignment structure, and th |
| 6159812 |
Reduced boron diffusion by use of a pre-anneal |
December 12, 2000 |
| A method for slowing the diffusion of boron ions in a CMOS structure includes a preanneal step which can be incorporated as part of a step in which silane is deposited across the surface of the wafer. After the last implant on a CMOS device, silane (SiH.sub.4) is deposited over the surfa |
| 6114211 |
Semiconductor device with vertical halo region and methods of manufacture |
September 5, 2000 |
| One method of forming a semiconductor device includes forming a gate electrode on a substrate and then forming a spacer adjacent to a sidewall of the gate electrode. An active region is formed in the substrate adjacent to the spacer and spaced apart from the gate electrode using a fi |
| 6110786 |
Semiconductor device having elevated gate electrode and elevated active regions and method of ma |
August 29, 2000 |
| A semiconductor device having an elevated gate electrode and elevated active regions and a process for manufacturing such a device is disclosed. In accordance with one embodiment a semiconductor device is formed by forming a gate insulating layer over a substrate and forming a photoresis |
| 6104077 |
Semiconductor device having gate electrode with a sidewall air gap |
August 15, 2000 |
| A semiconductor device having a gate electrode with a sidewall air gap is provided. In accordance with this embodiment, at least one gate electrode is formed over a substrate. A spacer is then formed adjacent an upper sidewall portion of the gate electrode such that an open area is left |
| 6075417 |
Ring oscillator test structure |
June 13, 2000 |
| An improved oscillator test structure is disclosed. A structure according to one embodiment includes an odd plurality of first transistor pairs formed on a predetermined area of a semiconductor substrate. The transistor pairs are electrically connected in a serial ring. The structure |
| 6074906 |
Complementary metal-oxide semiconductor device having source/drain regions formed using multiple |
June 13, 2000 |
| A CMOS semiconductor device having NMOS source/drain regions formed using multiple spacers has at least one NMOS region and at least one PMOS region. A first n-type dopant is selectively implanted into an NMOS active region of the substrate adjacent a NMOS gate electrode to form a first |
| 5977600 |
Formation of shortage protection region |
November 2, 1999 |
| The formation of a shortage protection region is disclosed. In one embodiment, a method includes three steps. In the first step, a first ion implantation is applied to form lightly doped regions within a semiconductor substrate adjacent to sidewalls of a gate over the substrate. In t |
| 5976925 |
Process of fabricating a semiconductor devise having asymmetrically-doped active region and gate |
November 2, 1999 |
| A semiconductor device having asymmetrically-doped gate electrode and active region and a process of fabricating such a device is provided. According to one embodiment of the invention, a polysilicon layer is formed over the substrate. The polysilicon layer is then implanted with a f |
| 5970349 |
Semiconductor device having one or more asymmetric background dopant regions and method of manuf |
October 19, 1999 |
| Semiconductor devices having one or more asymmetric background dopant regions and methods of fabrication thereof are provided. The asymmetric background dopant regions may be formed using a patterned mask with wider openings than conventional masks while substantially maintaining device |
| 5970311 |
Method and structure for optimizing the performance of a semiconductor device having dense trans |
October 19, 1999 |
| A method and structure for optimizing the performance of a semiconductor device having dense transistors. A method consistent with the present invention includes forming a first test structure on a first substrate portion. The first test structure includes a transistor having a gate |
| 5935766 |
Method of forming a conductive plug in an interlevel dielectric |
August 10, 1999 |
| A method of forming a conductive plug in an interlevel dielectric includes forming a lower dielectric layer over a semiconductor substrate. A first etch mask is formed over the lower dielectric layer and is patterned using a reticle. A first etch is applied through an opening in the firs |
| 5913116 |
Method of manufacturing an active region of a semiconductor by diffusing a dopant out of a sidew |
June 15, 1999 |
| In semiconductor device fabrication process, an active region of a semiconductor device is formed by diffusing a dopant out of a sidewall spacer. In the fabrication process, a gate electrode having a sidewall adjacent an active region is formed on a substrate and a doped spacer layer |
