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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Chauvel; Gerard
Address:
Antibes, FR
No. of patents:
100
Patents:


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Patent Number Title Of Patent Date Issued
8190861 Micro-sequence based security model May 29, 2012
A method and system for implementing a micro-sequence based security model in a processor. More particularly, micro-sequences and JSM hardware resources are employed to construct a security model invisible to applications, and when memory constraints are in place, extend a complex se
8185666 Compare instruction May 22, 2012
A processor executes an instruction that causes a comparison to be performed between contents of a first register and contents of a second register and between the contents of the first register and a predetermined value. The instruction is particularly useful for determining whether
8078842 Removing local RAM size limitations when executing software code December 13, 2011
An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions
8046748 Method and system to emulate an M-bit instruction set October 25, 2011
A method and system to emulate an M-bit instruction set. At least some of the illustrative embodiments are a method comprising fetching at least a portion of an instruction (the instruction from a first instruction set that is not directly executable by a processor), indexing into a tabl
8032891 Energy-aware scheduling of application execution October 4, 2011
A mobile device (10) manages tasks (18) using a scheduler (20) for scheduling tasks on multiple processors (12). To conserve energy, the set of tasks to be scheduled are divided into two (or more) subsets, which are scheduled according to different procedures. In a specific embodimen
8024554 Modifying an instruction stream using one or more bits to replace an instruction or to replace a September 20, 2011
A processor comprising fetch logic adapted to fetch instructions from memory and decode logic coupled to the fetch logic and adapted to decode the fetched instructions. If a bit in the decode logic is in a first state, a particular fetched instruction is skipped and a group of one or
7941790 Data processing apparatus, system and method May 10, 2011
A method for generating program code for translating high level code into instructions for one of a plurality of target processors comprises first determining a desired program code characteristic corresponding to a target processor. Then, selecting one or more predefined program code
7930689 Method and system for accessing indirect memories April 19, 2011
Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises
7840784 Test and skip processor instruction having at least one register operand November 23, 2010
A processor may execute a test and skip instruction that includes or otherwise specifies at least two operands that are used in a comparison operation. Based on the results of the comparison, the instruction that follows the test and skip instruction is "skipped." The test and skip i
7840782 Mixed stack-based RISC processor November 23, 2010
A processor (e.g., a co-processor) executes a stack-based instruction set and another instruction in a way that accelerates the execution of the stack-based instruction set, although code acceleration is not required under the scope of this disclosure. In accordance with at least some
7757223 Method and system to construct a data-flow analyzer for a bytecode verifier July 13, 2010
The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the
7757067 Pre-decoding bytecode prefixes selectively incrementing stack machine program counter July 13, 2010
A processor (e.g., a co-processor) comprising a decoder coupled to a pre-decoder, in which the decoder decodes a current instruction in parallel with the pre-decoder pre-decoding a subsequent instruction. In particular, the pre-decoder examines at least five Bytecodes in parallel wit
7743384 Method and system for implementing an interrupt handler June 22, 2010
A system for interrupt handling in Java is provided that includes an execution flow class, an execution flow scheduler, a Java virtual machine (JVM), and an interrupt handler class that extends the execution flow class. The execution flow class defines an execution flow execution met
7716673 Tasks distribution in a multi-processor including a translation lookaside buffer shared between May 11, 2010
A system comprises a first processor, a second processor coupled to the first processor, an operating system that executes exclusively only on the first processor and not on the second processor, and a middle layer software running on the first processor and that distributes tasks to run
7712098 Data transfer controlled by task attributes May 4, 2010
A digital system and method of operation is provided in which several processors (440, 450) are connected to a shared memory resource (460). Translation lookaside buffers (TLB) (400, 402) are connected to receive a request address (404a-n) from each respective processor. Each TLB has a
7634643 Stack register reference control bit in source operand of instruction December 15, 2009
A processor is disclosed herein that may execute an instruction that includes an immediate value and a reference to a register accessible to the processor. The instruction causes the processor to perform a test using the immediate value and the contents of the register referenced in
7624382 Method and system of control flow graph construction November 24, 2009
A method and system to build a control flow graph by execution of micro-sequences using hardware. Some illustrative embodiments are a processor comprising fetch logic that retrieves an instruction from a memory, the instruction being part of a program, and decode logic coupled to the
7587583 Method and system for processing a "WIDE" opcode when it is not used as a prefix for an immediat September 8, 2009
Methods and systems are provided for the selective use of a Java WIDE opcode as a prefix as defined in the instruction set of the Java virtual machine or performing a task assigned to the Java WIDE opcode. A Java WIDE opcode is fetched, a determination is made as to whether the Java
7574584 Splitting execution of a floating-point add instruction between an integer pipeline for performi August 11, 2009
In some embodiments, a processor includes fetch logic that fetches instructions, an integer pipeline, and a hardware state machine that is separate from and interacts with the integer pipeline. The instruction is executed partly in the integer pipeline according to software and partly
7565385 Embedded garbage collection July 21, 2009
An electronic system comprises a processor, memory coupled to the processor, and an application programming interface that causes an embedded garbage collection object to be active. The memory stores one or more objects that selectively have references from root objects. The embedded
7555611 Memory management of local variables upon a change of context June 30, 2009
A cache subsystem may comprise a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register. Local variables (e.g., Java local variables) may be stored in the data memory. The data memory preferably is adapted to s
7543014 Saturated arithmetic in a processing unit June 2, 2009
In some embodiments a system comprises an overflow control bit, a programmable saturation control bit, a processing unit, and a saturation unit coupled to the processing unit. A selection unit may select the output of the processing unit or the output of the saturation unit based on
7533250 Automatic operand load, modify and store May 12, 2009
A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a firs
7509391 Unified memory management system for multi processor heterogeneous architecture March 24, 2009
A multi-processor system 8 includes multiple processing devices, including DSPs (10), processor units (MPUs) (21), co-processors (30) and DMA channels (31). Some of the devices may include internal MMUs (19, 32) which allows the device (10, 21, 30, 31) to work with a large virtual ad
7506131 Reformat logic to translate between a virtual address and a compressed physical address March 17, 2009
In some embodiments, reformat logic comprises a plurality of registers and translation logic that accesses the registers. The translation logic receives a memory access targeting an application data structure that has a different format than accesses permitted to be provided to a device,
7500085 Identifying code for compilation March 3, 2009
A processor comprising fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions. The processor further comprises decode logic coupled to the fetch logic and adapted to process the set of instructions, and a clock coupled to the decode lo
7496930 Accessing device driver memory in programming language representation February 24, 2009
In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application software comprises instructions that initialize an application data structure (e.g., an object or array) usable by the applica
7493476 Method and system for obtaining an immediate operand of a bytecode for use by a micro-sequence February 17, 2009
A processor is provided that includes decode logic coupled to an instruction cache and a micro-sequence vector table including entries for each bytecode in an instruction set of the processor. The processor also includes a register coupled to the decode logic, wherein the register is
7434029 Inter-processor control October 7, 2008
A system includes a first processor coupled to a second processor. The first and second processors are coupled to memory. The first processor fetches and executes supported instructions until an unsupported instruction is detected. The second processor executes the unsupported instru
7434021 Memory allocation in a multi-processor system October 7, 2008
A process and associated system comprise pre-allocating a portion of memory in a first processor based upon a control input and determining in a second processor if the portion of the pre-allocated memory can satisfy a memory allocation request. Further, if a portion of pre-allocated
7395413 System to dispatch several instructions on available hardware resources July 1, 2008
A processor (e.g., a co-processor) capable of executing instructions sequentially, comprises at least two functional hardware resources. When two instructions that are consecutive in program order and are executed on two separate functional hardware resources, the execution of the two
7392269 Conditional garbage based on monitoring to improve real time performance June 24, 2008
A system comprising a counter adapted to monitor the memory consumption of the allocated memory resources. Upon reaching or surpassing the memory resource threshold provided, the counter may indicate the need for garbage collection. The garbage collector assesses the memory and relea
7386671 Smart cache June 10, 2008
A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a
7360060 Using IMPDEP2 for system commands related to Java accelerator hardware April 15, 2008
A processor (e.g., a co-processor) comprising a decoder adapted to decode instructions from a first instruction set in a first mode and a second instruction set in a second mode. A pre-decoder coupled to the decoder, and operates in parallel with the decoder, determines the mode of o
7330937 Management of stack-based memory usage in a processor February 12, 2008
A method is disclosed that comprises determining whether a data subsystem is to operate as cache memory or as scratchpad memory in which line fetches from external memory are suppressed and programming a control bit to cause the data subsystem to be operated as either a cache or scra
7295576 Transport packet parser November 13, 2007
A transport packet parser (42) includes a transport packet header decoder (50) for identifying a packet identifier (PID) and continuity counter (CC) associated with a current packet. The PID along with an enable (En) bit is input to an PID associative memory (52) in search mode to identi
7266824 Address space priority arbitration September 4, 2007
A digital system and method of operation is provided in which several processors (400[]) are connected to a shared resource (432). Each processor has a translation lookaside buffer (TLB) (310[]) that contains recently used page entries that each includes an access priority value. Acc
7260682 Cache memory usable as scratch pad storage August 21, 2007
A processor adapted to couple to external memory. The processor comprises a controller and data storage. The data storage is usable to store local variables and temporary data and is configurable to operate in either a cache policy mode in which a miss results in an access of the externa
7203797 Memory management of local variables April 10, 2007
A processor preferably comprises a processing core that generates memory addresses to access a main memory and on which a plurality of methods operate. Each method uses its own set of local variables. The processor also includes a cache subsystem comprising a multi-way set associative
7197623 Multiple processor cellular radio March 27, 2007
Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The Protocol Processor comprises a program part (30) including an incrementation register (31), a program memory
7174194 Temperature field controlled scheduling for processing systems February 6, 2007
A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build s
7162586 Synchronizing stack storage January 9, 2007
A system comprises a main stack, a local data stack and plurality of flags. The main stack comprises a plurality of entries and is located outside a processor's core. The local data stack is coupled to the main stack and is located internal to the processor's core. The local data sta
7146613 JAVA DSP acceleration by byte-code optimization December 5, 2006
A digital system and method of operation is which the digital system has a processor with a virtual machine environment for interpretively executing instructions. First, a sequence of instructions is received (404) for execution by the virtual machine. The sequence of instructions is
7120715 Priority arbitration based on current task and MMU October 10, 2006
A digital system and method of operation is provided in which several processors (740(0) 740(n)) are connected to a shared resource (750). Each processor has an access priority register (1410) that is loaded with an access priority value by software executing on the processor. A memory
7111177 System and method for executing tasks according to a selected scenario in response to probabilis September 19, 2006
A distributed processing system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to
7069415 System and method to automatically stack and unstack Java local variables June 27, 2006
A processor preferably comprises a processing core that generates memory addresses to access a memory and on which a plurality of methods operate, a cache coupled to the processing core, and a programmable register containing a pointer to a currently active method's set of local vari
7062304 Task based adaptative profiling and debugging June 13, 2006
A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build s
7058765 Processor with a split stack June 6, 2006
Methods and apparatuses are disclosed for implementing a processor with a split stack. In some embodiments, the processor includes a main stack and a micro-stack. The micro-stack preferably is implemented in the core of the processor, whereas the main stack may be implemented in areas th
6996683 Cache coherency in a multi-processor system February 7, 2006
A system comprises a first processor having cache memory, a second processor having cache memory and a coherence buffer that can be enabled and disabled by the first processor. The system also comprises a memory subsystem coupled to the first and second processors. For a write transa
6957315 TLB lock and unlock operation October 18, 2005
A digital system and method of operation is provided in which several processing resources (340) and processors (350) are connected to a shared translation lookaside buffer (TLB) (300, 310(n)) of a memory management unit (MMU) and thereby access memory and devices. These resources can be
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