| Patent Number |
Title Of Patent |
Date Issued |
| 7555667 |
Programmable logic device integrated circuit with dynamic phase alignment capabilities and share |
June 30, 2009 |
| Adjustable transceiver circuitry is provided for programmable integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data signals. The transceiver circuitry supports a phase-locked-loop source synchronous mode that can |
| 7490209 |
Fully buffered DIMM system and method with hard-IP memory controller and soft-IP frequency contr |
February 10, 2009 |
| A system and method for memory control. The system includes a hard-IP memory controller, a soft-IP frequency conversion system, and an interface system. The soft-IP frequency conversion system is coupled to the hard-IP memory controller, and is capable of being programmed to convert |
| 7417452 |
Techniques for providing adjustable on-chip termination impedance |
August 26, 2008 |
| Techniques are provided for individually adjusting the on-chip termination impedance that is generated by input and output (IO) buffers in an input/output (IO) bank on an integrated circuit. The IO buffers in an IO bank can generate different on-chip termination impedances. And as a |
| 7378868 |
Modular I/O bank architecture |
May 27, 2008 |
| A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O bank type are compatible within the same programmable device and between different type |
| 7324405 |
DQS postamble filtering |
January 29, 2008 |
| Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or di |
| 7282973 |
Enhanced DLL phase output scheme |
October 16, 2007 |
| A method and system using a delay-locked loop (DLL) to provide multiple phase locked outputs in discrete phase intervals is disclosed. In one embodiment, a reference clock signal is transmitted through a delay chain having a plurality of delay elements. The delay chain is capable of |
| 7031222 |
DQS postamble filtering |
April 18, 2006 |
| Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or di |
