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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Chang; Shih-Tzung
Address:
Taichung, TW
No. of patents:
3
Patents:












Patent Number Title Of Patent Date Issued
7528478 Semiconductor devices having post passivation interconnections and a buffer layer May 5, 2009
An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pat
7128821 Electropolishing method for removing particles from wafer surface October 31, 2006
An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and
7026233 Method for reducing defects in post passivation interconnect process April 11, 2006
A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer










 
 
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