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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Chang; Mike F.
Address:
Cupertino, CA
No. of patents:
31
Patents:












Patent Number Title Of Patent Date Issued
7633140 Inverted J-lead for power devices December 15, 2009
A semiconductor package includes a lead frame having a plurality of leads and a lead frame pad, the lead frame pad including a die coupled thereto, at least one of the plurality of leads having an external portion sloped upwards relative to a bottom surface of the package, metal connecto
7208818 Power semiconductor package April 24, 2007
A semiconductor package including a relatively thick lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die coupled thereto, bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum, and a resin body
6444527 Method of operation of punch-through field effect transistor September 3, 2002
A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source
6277695 Method of forming vertical planar DMOSFET with self-aligned contact August 21, 2001
The metal contact to the source and body regions in a vertical planar DMOSFET is formed by fabricating a sidewall spacer on the gate of the MOSFET. With the metal contact self-aligned to the gate in this way, the lateral dimension of each of the cells in the DMOSFET can be significantly
6090716 Method of fabricating a field effect transistor July 18, 2000
In the present method, a semiconductor substrate is provided with an epitaxial layer thereon. A source/drain region is provided in a portion of the epitaxial layer, and a plurality of trenches are etched in the epitaxial layer and extend into the substrate, to define a plurality of m
6069043 Method of making punch-through field effect transistor May 30, 2000
A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source
5998834 Long channel trench-gated power MOSFET having fully depleted body region December 7, 1999
A trenched-gate power MOSFET includes a body region that is formed within a mesa between adjacent gate trenches. The doping concentration of the body region is established such that the body region does not fully deplete at normal drain voltages. The MOSFET also includes a gate which is
5981344 Trench field effect transistor with reduced punch-through susceptibility and low R.sub.DSon November 9, 1999
To reduce susceptibility to punchthrough, the channel region of the P body region of a trench field effect transistor is formed in a layer of lightly doped epitaxial silicon. As a result, the channel region has less counterdoping from the background epitaxial silicon and has a greater ne
5929481 High density trench DMOS transistor with trench bottom implant July 27, 1999
A trenched DMOS transistor overcomes the problem of a parasitic JFET at the trench bottom (caused by deep body regions extending deeper than the trench) by providing a doped trench bottom implant region at the bottom of the trench and extending into the surrounding drift region. This tre
5923979 Planar DMOS transistor fabricated by a three mask process July 13, 1999
A planar DMOS power transistor (MOSFET) fabricated using only three masking steps, resulting in a significant reduction in fabrication cost. The resulting device is in terms of operations similar to prior art devices formed using more masking steps. Both the source and body regions are
5917216 Trenched field effect transistor with PN depletion barrier June 29, 1999
A trenched MOSFET in its on-state conducts current through an accumulation region and through an inverted depletion barrier layer located along the trench sidewalls. Blocking is achieved by gate control depletion of the adjacent region and by the depletion barrier layer (having the appea
5910669 Field effect Trench transistor having lightly doped epitaxial region on the surface portion ther June 8, 1999
A DMOS field effect transistor having its gate electrode located in a trench includes a lightly doped epitaxial layer overlying the usual epitaxial layer. The trench penetrates only part way through the upper epitaxial layer which is more lightly doped than is the underlying lower ep
5821583 Trenched DMOS transistor with lightly doped tub October 13, 1998
A trenched DMOS transistor has significantly reduced on-resistance. A lightly doped P tub is formed surrounding the P+ body region in order to enhance avalanche breakdown. Thus the epitaxial layer resistivity can be decreased to reduce device on-resistance, while the desired breakdown
5767578 Surface mount and flip chip technology with diamond film passivation for total integated circuit June 16, 1998
An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat
5757081 Surface mount and flip chip technology for total integrated circuit isolation May 26, 1998
An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat
5753529 Surface mount and flip chip technology for total integrated circuit isolation May 19, 1998
An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat
5750416 Method of forming a lateral field effect transistor having reduced drain-to-source on-resistance May 12, 1998
A power field effect transistor has a laterally extending channel region which is not formed by double diffusion. The channel region may be formed in epitaxial silicon which is not doped after being grown. The drain electrode of the transistor is disposed on a bottom surface of the s
5689128 High density trenched DMOS transistor November 18, 1997
The cell density of a trenched DMOS transistor is increased by overcoming the problem of lateral diffusion of deep P+body regions. This problem is solved in three versions. In a first version, the deep P+body region is formed using a high energy implant into a single epitaxial layer. In
5639676 Trenched DMOS transistor fabrication having thick termination region oxide June 17, 1997
A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The
5629543 Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness May 13, 1997
A trench DMOS transistor includes a buried layer region formed between the drain region and overlying drift region and having a doping type the same as that of the drift region and drain region. The buried layer region is more highly doped than the drain region or drift regions and is fo
5592005 Punch-through field effect transistor January 7, 1997
A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source
5578851 Trenched DMOS transistor having thick field oxide in termination region November 26, 1996
A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The
5558313 Trench field effect transistor with reduced punch-through susceptibility and low R.sub.DSon September 24, 1996
To reduce susceptibility to punchthrough, the channel region of the P body region of a trench field effect transistor is formed in a layer of lightly doped epitaxial silicon. As a result, the channel region has less counterdoping from the background epitaxial silicon and has a greater ne
5532179 Method of making a field effect trench transistor having lightly doped epitaxial region on the s July 2, 1996
A DMOS field effect transistor having its gate electrode located in a trench includes a lightly doped epitaxial layer overlying the usual epitaxial layer. The trench penetrates only part way through the upper epitaxial layer which is more lightly doped than is the underlying lower ep
5486772 Reliability test method for semiconductor trench devices January 23, 1996
The present invention detects defects near the gate/trench-surface interface of trench transistors. Defects near this interface which cause long term reliability problems generally also result in charges being trapped near the interface. In accordance with one embodiment of the prese
5468982 Trenched DMOS transistor with channel block at cell trench corners November 21, 1995
A trenched DMOS transistor has improved device performance and production yield. During fabrication the cell trench corners, i.e. the areas where two trenches intersect, are covered on the principal surface of the integrated circuit substrate with a blocking photoresist layer during the
5439842 Low temperature oxide layer over field implant mask August 8, 1995
A thin base oxide is disposed over both an active area and also over a field area of a substrate. A thin silicon-nitride layer is then formed over the base oxide in the active area to protect the underlying substrate from oxygen and/or water vapor during a subsequent field oxidation step
5426325 Metal crossover in high voltage IC with graduated doping control June 20, 1995
Non-uniformly doped regions are formed adjacent to semiconductor junctions which underlie high voltage crossovers. The non-uniformly doped regions prevent junction breakdown caused by strong electric fields. The voltage drop between a crossover and an element of an integrated circuit is
5328866 Low temperature oxide layer over field implant mask July 12, 1994
A thin base oxide is disposed over both an active area and also over a field area of a substrate. A thin silicon-nitride layer is then formed over the base oxide in the active area to protect the underlying substrate from oxygen and/or water vapor during a subsequent field oxidation step
5316959 Trenched DMOS transistor fabrication using six masks May 31, 1994
A trenched DMOS transistor is fabricated using six masking steps. One masking step defines both the P+ regions and the active portions of the transistor which are masked using a LOCOS process. The LOCOS process also eliminates the poly stringer problem present in prior art structures by
5132753 Optimization of BV and RDS-on by graded doping in LDD and other high voltage ICs July 21, 1992
Transistor structure using a lightly doped drain (LDD) technique are disclosed. The present invention provides a reduced on-resistance in the LDD region, while retaining substantially all the high breakdown voltage advantage of the LDD technique. The advantage of the present invention is










 
 
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