| Patent Number |
Title Of Patent |
Date Issued |
| 7439141 |
Shallow trench isolation approach for improved STI corner rounding |
October 21, 2008 |
| A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. |
| 7374654 |
Method of making an organic memory cell |
May 20, 2008 |
| A method of making an organic memory cell which comprises two electrodes with a controllably conductive media between the two electrodes is disclosed. The present invention involves providing a dielectric layer having formed therein one or more first electrode pads; removing a portio |
| 7361588 |
Etch process for CD reduction of arc material |
April 22, 2008 |
| A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can be utilized to for |
| 7015504 |
Sidewall formation for high density polymer memory element array |
March 21, 2006 |
| Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side |
| 6979619 |
Flash memory device and a method of fabrication thereof |
December 27, 2005 |
| In a first aspect of the present invention, a method of fabricating a flash memory device is disclosed. The method comprises the steps of providing a portion of a dual gate oxide in a periphery area of the memory device and then simultaneously providing a dual gate oxide in a core area o |
| 6900488 |
Multi-cell organic memory element and methods of operating and fabricating |
May 31, 2005 |
| The present invention provides a multi-cell organic memory device that can operate as a non-volatile memory device having a plurality of multi-cell structures constructed within the memory device. A lower electrode can be formed, wherein one or more passive layers are formed on top of th |
| 6878961 |
Photosensitive polymeric memory elements |
April 12, 2005 |
| A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer |
| 6864556 |
CVD organic polymer film for advanced gate patterning |
March 8, 2005 |
| A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a patt |
| 6836398 |
System and method of forming a passive layer by a CMP process |
December 28, 2004 |
| The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is p |
| 6825060 |
Photosensitive polymeric memory elements |
November 30, 2004 |
| A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer |
| 6815292 |
Flash memory having improved core field isolation in select gate regions |
November 9, 2004 |
| A flash memory array having improved core field isolation in select gate regions via shallow trench isolation and field isolation implant after liner oxidation is disclosed. The flash memory array includes a core area and a periphery area, wherein the core area further includes a select |
| 6812077 |
Method for patterning narrow gate lines |
November 2, 2004 |
| Patterning of a gate line is terminated prior to etching completely through the conductive layer from which it is patterned. Surfaces of the conductive layer are then reacted in a reactive atmosphere, and the reacted surfaces are removed, creating a narrow gate line. The protection p |
| 6806165 |
Isolation trench fill process |
October 19, 2004 |
| A method for filling an isolation trench structure during a semiconductor fabrication process is disclosed. The method includes a two-step deposition process that includes depositing a silicon-rich liner on the trench surface, and thereafter, filling the isolation trenches with an ox |
| 6797552 |
Method for defect reduction and enhanced control over critical dimensions and profiles in semico |
September 28, 2004 |
| A layer of material is patterned anisotropically using a bi-layer hardmask structure. Residual photoresist from a photoresist mask used to pattern an upper layer of the bi-layer hardmask is removed prior to patterning of the polysilicon layer. Passivation agents are later introduced from |
| 6787458 |
Polymer memory device formed in via opening |
September 7, 2004 |
| One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, form |
| 6773954 |
Methods of forming passive layers in organic memory cells |
August 10, 2004 |
| Methods of making an organic memory cell made of two electrodes with a controllably conductive media between the two electrodes are disclosed. The controllably conductive Media contains an organic semiconductor layer and passive layer. In particular, novel methods of forming a electrode |
| 6764949 |
Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabric |
July 20, 2004 |
| A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The |
| 6753247 |
Method(s) facilitating formation of memory cell(s) and patterned conductive |
June 22, 2004 |
| A methodology for forming a memory cell is disclosed, wherein an organic polymer layer is formed over a conductive layer and an electrode layer is formed over the organic polymer layer. A first via is etched into the electrode and organic polymer layers, and a dielectric material is appl |
| 6750127 |
Method for fabricating a semiconductor device using amorphous carbon having improved etch resist |
June 15, 2004 |
| An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides |
| 6727195 |
Method and system for decreasing the spaces between wordlines |
April 27, 2004 |
| A method and system for providing a semiconductor device is disclosed. The method and system include providing a semiconductor substrate and providing a plurality of lines separated by a plurality of spaces. Each of the plurality of spaces preferably has a first width that is less than a |
| 6642148 |
RELACS shrink method applied for single print resist mask for LDD or buried bitline implants usi |
November 4, 2003 |
| The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The semiconductor substrate is doped wi |
| 6638358 |
Method and system for processing a semiconductor device |
October 28, 2003 |
| The present invention is a method and system for processing a semiconductor device, the semiconductor device comprising at least two gate stacks and a spacer gap. The method and system comprise utilizing a spin-on technique at the transistor device level to provide an oxide spacer in the |
| 6610580 |
Flash memory array and a method and system of fabrication thereof |
August 26, 2003 |
| In a first aspect of the present invention, a flash memory array is disclosed. The flash memory array comprises a substrate comprising active regions, wherein the active regions are defined by a layer of nitride, the layer of nitride including a top surface. The flash memory array furthe |
| 6566230 |
Shallow trench isolation spacer for weff improvement |
May 20, 2003 |
| A method for performing trench isolation during semiconductor device fabrication is disclosed. The method includes patterning a hard mask to define active areas and isolations areas on a substrate, and forming spacers along edges of the hard mask. Trenches are then formed in the subs |
| 6509232 |
Formation of STI (shallow trench isolation) structures within core and periphery areas of flash |
January 21, 2003 |
| STI (shallow trench isolation) structures are formed for a flash memory device fabricated within an semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein. |
| 6475847 |
Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer |
November 5, 2002 |
| A method for shrinking a semiconductor device and minimizing auto-doping problem is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking o |
| 6472327 |
Method and system for etching tunnel oxide to reduce undercutting during memory array fabricatio |
October 29, 2002 |
| A method and system for etching gate oxide during transistor fabrication is disclosed. The method and system begin by depositing a gate oxide on a substrate, followed by a deposition of a tunnel oxide mask over a portion of the gate oxide. The method and system further include performing |
| 6448594 |
Method and system for processing a semiconductor device |
September 10, 2002 |
| In a first aspect of the present invention, a semiconductor device is disclosed. The semiconductor device comprises at least two gate stacks, each gate stack having two sides and oxide spacers on each of the two sides of each of the at least two gate stacks, wherein at least one of the |
| 6445051 |
Method and system for providing contacts with greater tolerance for misalignment in a flash memo |
September 3, 2002 |
| A method and system for providing a plurality of contacts in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and a plurality of field insulating regions adjacent to a portion of the plurality of gate stacks. The method and system include pr |
| 6431182 |
Plasma treatment for polymer removal after via etch |
August 13, 2002 |
| A method and article of manufacture of a via in a semiconductor layered device. The method can include applying an OH/H containing plasma, such as H.sub.2 O or O.sub.2 or a forming gas, to a via which has been etched in a layer of the device. A mixture of oxygen and fluorine-based plasma |
| 6420752 |
Semiconductor device with self-aligned contacts using a liner oxide layer |
July 16, 2002 |
| A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The |
| 6420224 |
Stepper alignment mark formation with dual field oxide process |
July 16, 2002 |
| A semiconductor photomask set for producing wafer alignment accuracy in a semiconductor fabrication process. The photomask set produces an alignment mark that is accurate for subsequent fabrication after undergoing a dual field oxide (FOX) fabrication process. Prior arts methods have |
| 6400030 |
Self-aligning vias for semiconductors |
June 4, 2002 |
| An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the firs |
| 6326310 |
Method and system for providing shallow trench profile shaping through spacer and etching |
December 4, 2001 |
| A system and method for providing a trench in a material using semiconductor processing is disclosed. In one aspect, the method and system include (a) providing a spacer, (b) etching the material, and (c) repeating steps (a) and (b) a sufficient number of times to achieve a desired p |
| 6306706 |
Method and system for fabricating a flash memory array |
October 23, 2001 |
| A method and system for fabricating a flash memory array comprising a core area and a periphery area is disclosed. The method and system comprises depositing a layer of poly2 over the core area and the periphery area, selectively etching the core area, and selectively etching the poly2 o |
| 6249036 |
Stepper alignment mark formation with dual field oxide process |
June 19, 2001 |
| A semiconductor photomask set for producing wafer alignment accuracy in a semiconductor fabrication process. The photomask set produces an alignment mark that is accurate for subsequent fabrication after undergoing a dual field oxide (FOX) fabrication process. Prior arts methods have |
| 6200884 |
Method for shaping photoresist mask to improve high aspect ratio ion implantation |
March 13, 2001 |
| A method for making a ULSI MOSFET chip includes masking areas such as transistor gates with photoresist mask regions. Prior to ion implantation, the top shoulders of the mask regions are etched away, to round off the shoulders. This promotes subsequent efficient quasi-vertical ion im |
| 6124201 |
Method for manufacturing semiconductors with self-aligning vias |
September 26, 2000 |
| An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the firs |
| 6093967 |
Self-aligned silicide contacts formed from deposited silicon |
July 25, 2000 |
| Self-aligned silicide contacts having a height that is at least about equal to the gate height are formed by depositing silicon over active regions of the substrate, depositing a refractory metal over the silicon, and heating the silicon and the refractory metal. The deposited silicon ma |
| 5965934 |
Processing techniques for achieving production-worthy, low dielectric, low interconnect resistan |
October 12, 1999 |
| The interconnects in a semiconductor device contacting metal lines comprise a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof A tri-layer resist structure i |
| 5945352 |
Method for fabrication of shallow isolation trenches with sloped wall profiles |
August 31, 1999 |
| The present invention provides a method for fabricating shallow isolation trenches with sloped walls in semiconductor wafers. The method uses a conformal polysilicon layer to form an etch barrier over trench regions in a semiconductor substrate. This etch barrier has areas of varying |
| 5679608 |
Processing techniques for achieving production-worthy, low dielectric, low dielectric, low inter |
October 21, 1997 |
| The interconnects in a semiconductor device contacting metal lines includes a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof. A tri-layer resist structure |
| 5559055 |
Method of decreased interlayer dielectric constant in a multilayer interconnect structure to inc |
September 24, 1996 |
| The RC time constant of a semiconductor device is reduced by decreasing the capacitance C. The decrease in capacitance is achieved by replacing the interlayer silicon dioxide (dielectric constant of 4.0) with air (dielectric constant of 1.0). Alternatively, the air space can also be |
| 5550405 |
Processing techniques for achieving production-worthy, low dielectric, low interconnect resistan |
August 27, 1996 |
| The interconnects in a semiconductor device contacting metal lines comprise a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof. A tri-layer resist structure |
