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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Chang; Chun-Yen
Address:
Hsinchu, TW
No. of patents:
22
Patents:












Patent Number Title Of Patent Date Issued
7977687 Light emitter device July 12, 2011
A light emitting device (LED) structure formed on a Group IV-based semiconductor substrate is provided. The LED structure includes a Group IV-based substrate, an AlN nucleation layer formed on the Group IV-based substrate, a GaN epitaxial layer formed on the AlN nucleation layer, a d
7888152 Method of forming laterally distributed LEDs February 15, 2011
A method of forming laterally distributed light emitting diodes (LEDs) is disclosed. A first buffer layer with a first type of conductivity is formed on a semiconductor substrate, and a dielectric layer is formed on the first buffer layer. The dielectric layer is patterned to form a firs
7643103 Backlight module having through hole with heat conductive metal plate therein and liquid crystal January 5, 2010
A backlight module and a liquid crystal display (LCD) both have a heat conductive structure for reducing the non-uniformity phenomenon of display. The backlight module comprises a frame, a reflective sheet, a heat-conductive plate, and a circuit board, wherein the frame has a bottom
7415257 Dual-band mixer and its design flow August 19, 2008
In the dual-band mixer of this invention, a current combined load is presented and is shared by two separate working frequency bands. In the invented dual-band mixer, a switch is provided to connect and disconnect an adjust capacitor series to the load inductors. By determining the c
7071087 Technique to grow high quality ZnSe epitaxy layer on Si substrate July 4, 2006
A technique to grow high quality and large area ZnSe layer on Si substrate is provided, comprising growing Ge.sub.xSi.sub.1-x/Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and finally growing a ZnSe film on top Ge buffer layers.Two
7018883 Dual work function gate electrodes March 28, 2006
Methods of manufacturing transistor gate electrodes including, in one embodiment, forming a metal layer over first and second regions of a substrate, wherein the first and second regions have different first and second dopant types, respectively. A semiconductor layer is formed over
6495432 Method of improving a dual gate CMOS transistor to resist the boron-penetrating effect December 17, 2002
A method of reducing the boron-penetrating of effect in a CMOS transistor provides a silicon substrate, which comprises an isolating area, an active area and a gate oxide layer formed on the silicon substrate in the active layer. A polysilicon layer is then deposited on the silicon subst
6432786 Method of forming a gate oxide layer with an improved ability to resist the process damage August 13, 2002
A method of forming a gate oxide layer with improved ability to resist process damage increases the reliability and yield of a transistor device. First, a nitrogen-containing gate oxide layer is formed on an element area of a silicon substrate. Then, a polysilicon layer is deposited on t
6426246 Method for forming thin film transistor with lateral crystallization July 30, 2002
A method for forming thin film transistor with lateral crystallization. The method at least includes the following steps. First of all, an insulation substrate is provided. Then, an amorphous silicon layer is provided on the insulation substrate. The seeds are formed by annealing a porti
6306697 Low temperature polysilicon manufacturing process October 23, 2001
A low temperature polysilicon manufacturing method. A system for performing physical vapor deposition is used to form an amorphous silicon film with micro-crystals therein. The amorphous silicon film is annealed at a temperature between 400.degree. C. to 500.degree. C. for about 6 to 16
6174367 Epitaxial system January 16, 2001
An epitaxial system is provided for performing an epitaxial growth of IIIA-VA compound on the wafer substrate. The epitaxial system includes a first reaction region for providing a plasma of a first reactant, a second reaction region for epitaxially reacting the plasma of the first react
6080607 Method for manufacturing a transistor having a low leakage current June 27, 2000
The invention provides a method for manufacturing a transistor having a low leakage current. In general, spacers must be formed to isolate a gate from a subsequently-formed drain, thereby reducing a leakage current. In the invention, the spacers are formed on the vertical sides of the ga
5985709 Process for fabricating a triple-well structure for semiconductor integrated circuit devices November 16, 1999
A triple-well structure for semiconductor IC devices such as an SRAM IC device and a process for its fabrication, that allows for improved data storage stability as well as improved immunity capability against interference from device I/O bouncing and alpha particles. The triple-well
5943560 Method to fabricate the thin film transistor August 24, 1999
Ultrahigh vacuum chemical vapor deposition (UHV/CVD) and chemical mechanical polishing (CMP) systems are used in a method which can fabricate polycrystalline silicon (poly-Si) and polycrystalline silicon-germanium (poly-Si.sub.1-x -Ge.sub.x) thin film transistors at low temperature a
5858826 Method of making a blanket N-well structure for SRAM data stability in P-type substrates January 12, 1999
SRAMs conventionally formed on N-type substrates are instead formed on P-type substrates which have had the surface layer of the substrate converted to a blanket N-type well region. Preferably, the blanket N-type well region is formed by ion implantation of phosphorus ions to a dosage
5786244 Method for making GaAs-InGaAs high electron mobility transistor July 28, 1998
A GaAs-InGaAs high electron mobility transistor includes: a GaAs substrate; a GaAs buffer layer overlaying on the GaAs substrate; a graded InGaAs channel overlaying on the GaAs layer; a GaAs spacer layer overlaying on the graded InGaAs channel layer; a .delta.-doping layer overlaying on
5766967 Method for fabricating a submicron T-shaped gate June 16, 1998
A method for fabricating submicron T-shaped gates for the field-effect transistors disclosed, which can be accomplished by using a tri-layer positive photoresist with a single electron beam exposure and a single development step. Therefore, the cost can be reduced and the yield can be
5674777 Method for forming silicon-boron binary compound layer as boron diffusion source in silicon elec October 7, 1997
The present invention is related to a method for fabricating a silicon electronic device having a boron diffusion source layer, includes steps of: a) providing a silicon substrate; b) depositing a silicon layer on said silicon substrate; and c) growing a silicon-boron binary compound
5658806 Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration August 19, 1997
A method for fabricating a self-aligned thin-film transistor, in accordance with the present invention, first involves forming a gate electrode on an insulating layer. Next, a gate dielectric layer is formed to enclose the gate electrode. Subsequently, a semiconductor layer, a conducting
5652440 GaAs-InGaAs high electron mobility transistor July 29, 1997
A GaAs-InGaAs high electron mobility transistor includes: a GaAs substrate; a GaAs buffer layer overlaying on the GaAs substrate; a graded InGaAs channel overlaying on the GaAs layer; a GaAs spacer layer overlaying on the graded InGaAs channel layer; a .delta.-doping layer overlaying on
5554985 Method for scanning keypad architecutre employing power source and ground of digital electronic September 10, 1996
A scanning method of keypad architectures utilizing power pin V.sub.DD and ground pin GND of an integrated circuit device is disclosed. The integrated circuit device has a number of row pins and column pins, a power pin and a ground pin, and a number of pins for other functions of th
5541801 Low-voltage gate trigger SCR (LVGTSCR) ESD protection circuit for input and output pads July 30, 1996
An electrostatic discharge (ESD) protection circuit for eliminating the stress of electrostatic discharge and preventing destruction of an internal semiconductor circuit. A first low-voltage gate trigger silicon controlled rectifier anode and anode gate, a second low-voltage gate tri










 
 
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