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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Chang; Ching-Yu
Address:
Yilan Hsien, TW
No. of patents:
18
Patents:












Patent Number Title Of Patent Date Issued
7097945 Method of reducing critical dimension bias of dense pattern and isolation pattern August 29, 2006
A method of reducing a critical dimension ("CD") bias between a dense pattern and an isolation pattern is disclosed. The method includes a first step of providing a mask having a dense pattern, an isolation pattern and the other area of the mask is transparent, in which mask the dens
7094662 Overlay mark and method of fabricating the same August 22, 2006
A method of forming an overlay mark is provided. A first material layer is formed on a substrate, and then a first trench serving as a trench type outer mark is formed in the first material layer. The first trench is partially filled with the first deposition layer. A second material is
7064035 Mask ROM and fabrication thereof June 20, 2006
A Mask ROM and a method for fabricating the same are described. The Mask ROM comprises a substrate, a plurality of gates on the substrate, a gate oxide layer between the gates and the substrate, a plurality of buried bit lines in the substrate between the gates, an insulator on the burie
7051800 Hot plate cooling system May 30, 2006
A cooling system for a hot plate. The cooling system includes a plurality of pipelines inside the hot plate. Each pipeline has an inlet and an outlet. The inlet permits a cooling fluid to enter and the outlet permits the cooling fluid to leave. The cooling fluid running inside the pi
6998316 Method for fabricating read only memory including a first and second exposures to a photoresist February 14, 2006
A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit region has transistors. A precise layer having a plurality of first openings is formed in th
6916713 Code implantation process July 12, 2005
The present invention provides a code implantation process for the mask read only memory (MROM). A gate oxide layer and a wordline are formed sequentially over a substrate having a buried bitline, with a cap layer formed on the top of the wordline. A dielectric layer is formed on the
6861176 Hole forming by cross-shape image exposure March 1, 2005
A method of forming holes in a layer through a cross-shape image exposure. The method includes removing a section from each corner of the rectangular patterns on a photomask to form cross-shape patterns so that circular or elliptical contact holes are formed on a photoresist layer after
6806535 Non-volatile memory and fabricating method thereof October 19, 2004
A method of fabricating a non-volatile memory is provided. A longitudinal strip of stacked layer is formed over a substrate. The longitudinal strip is a stacked layer including a gate dielectric layer, a conductive layer and a cap layer. A buried bit line is formed in the substrate on ea
6794280 Method of fabricating non-volatile memory September 21, 2004
A method of fabricating a non-volatile memory is provided. A longitudinal strip of stacked layer is formed over a substrate. The longitudinal strip is a stacked layer comprising a gate dielectric layer, a conductive layer and a cap layer. A buried bit line is formed in the substrate on e
6777762 Mask ROM structure having a coding layer between gates and word lines August 17, 2004
A Mask ROM and a method for fabricating the same are described. The Mask ROM comprises a substrate, a plurality of gates on the substrate, a gate oxide layer between the gates and the substrate, a plurality of buried bit lines in the substrate between the gates, an insulator on the burie
6734064 Method for fabricating read only memory including forming masking layers with openings and pre-c May 11, 2004
A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit region has transistors. A precise layer having a plurality of first openings is formed in th
6720210 Mask ROM structure and manufacturing method thereof April 13, 2004
A mask read-only-memory structure and its method of manufacture are provided. The structure includes a substrate, a buried bit line in the substrate and a patterned stack layer covering a portion of the upper surface of the substrate. The stack layer includes a first dielectric layer
6607674 Method of repairing a phase shifting mask August 19, 2003
A phase shifting mask repair process is described. The process uses an etching gas or a hydrofluoric acid solution to etch the quartz substrate and the characteristics of the phase shifter layer being only slightly etched when clean with a NH.sub.3 /H.sub.2 O.sub.2 /H.sub.2 O.sub.2 s
6576515 Method of forming transistor gate June 10, 2003
A method of forming a transistor gate. A substrate having a source/drain terminals, a gate dielectric layer, a lower section of a floating gate, a dielectric layer over the substrate is provided. The dielectric layer has an opening that exposes a portion of the upper surface of the lower
6458657 Method of fabricating gate October 1, 2002
A method of fabricating a gate. A gate dielectric layer is formed, and a lower portion of a floating gate is formed encompassed by a first dielectric layer. Second dielectric layers with different etching rates are formed to cover the upper portion of the floating gate and the first
6448605 Method of fabricating gate September 10, 2002
A method of fabricating a gate is described. A first dielectric layer having a first opening is formed on a substrate. A gate dielectric layer is formed in the opening. A lower portion of a floating gate is formed on the gate dielectric layer. A source/drain region is formed in the s
6399259 Method of forming alignment marks for photolithographic processing June 4, 2002
An alignment method for photolithography, especially for forming an alignment marker on a substrate after ion implantation. A substrate that includes a device region and an alignment mark region is provided. A first patterned photoresist layer is formed over the substrate. The first
6300196 Method of fabricating gate October 9, 2001
A method of fabricating a gate is described. A first dielectric layer having a first opening is formed on a substrate. A gate dielectric layer is formed in the opening. A lower portion of a floating gate is formed on the gate dielectric layer. A source/drain region is formed in the s










 
 
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