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Inventor: Chang; Chih-Wei David
Address: Saratoga, CA
No. of patents: 4
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 6446224 |
Method and apparatus for prioritizing and handling errors in a computer system |
September 3, 2002 |
| A computer system includes a central processing unit and a memory management unit having a plurality of functional units, such as a memory interface unit, a remote interface unit, a cache interface unit, and a translation unit. Each functional unit has a low priority error queue for |
| 5893931 |
Lookaside buffer for address translation in a computer system |
April 13, 1999 |
| A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (TLB) and, possibly, a translation table held in memory and implemented as a B-tree data structure. The TLB is initially searched for a |
| 5835962 |
Parallel access micro-TLB to speed up address translation |
November 10, 1998 |
| A memory management unit (MMU) includes a translation lookaside buffer capable of simultaneously servicing three requests supplied to the MMU by an instruction cache and two data caches, respectively. Also, an arbiter selects one of several pending requests from sources of different |
| 5680566 |
Lookaside buffer for inputting multiple address translations in a computer system |
October 21, 1997 |
| A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (TLB) and, possibly, a translation table held in memory and implemented as a B-tree data structure. The TLB is initially searched for a |
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