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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Chan; Tsiu Chiu
Address:
Carrollton, TX
No. of patents:
39
Patents:












Patent Number Title Of Patent Date Issued
RE40579 Structure for transistor devices in an SRAM cell November 25, 2008
An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate tran
RE37769 Methods for fabricating memory cells and load elements June 25, 2002
A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the
7112468 Stacked multi-component integrated circuit microprocessor September 26, 2006
An apparatus and method for fabricating a microprocessor comprising a first chip (12) having an active face (30) including a central processing unit and a second chip (14) having an active face (32) electrically connected to the active face of the first chip (12), wherein the second
7026718 Stacked multi-component integrated circuit microprocessor April 11, 2006
An apparatus and method for fabricating-a microprocessor comprising a first chip (12) having an active face (30) including a central processing unit and a second chip (14) having an active face (32) electrically connected to the active face of the first chip (12), wherein the second
6750775 Integrated sensor having plurality of released beams for sensing acceleration and associated met June 15, 2004
An integrated circuit and method are provided for sensing activity such as acceleration in a predetermined direction of movement. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to and positioned adjacent t
6518620 EEPROM memory cell with increased dielectric integrity February 11, 2003
A memory cell for an EEPROM memory is fabricated to provide increased oxide thickness at the edge of the tunnel oxide and under the edges of the polysilicon capacitor plate in order to improve the dielectric integrity of the capacitor structure. In one embodiment using a silicided po
6486007 Method of fabricating a memory cell for a static random access memory November 26, 2002
A method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters
6455884 Radiation hardened semiconductor memory with active isolation regions September 24, 2002
A radiation hardened memory device includes active gate isolation structures placed in series with conventional oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer
6381115 Redundant electric fuses April 30, 2002
A redundant electric fuse circuit is provided that includes a plurality of fuses coupled in series and each having a fuse control device operable for generating a current through each fuse sufficient to blow the fuse. A first fuse control signal is activated to generate a sufficient curr
6295224 Circuit and method of fabricating a memory cell for a static random access memory September 25, 2001
A circuit and method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic
6271063 Method of making an SRAM cell and structure August 7, 2001
A six transistor static random access memory (SRAM) cell with thin-film pull-up transistors and method of making the same includes providing two bulk silicon pull-down transistors of a first conductivity type, two active gated pull-up thin-film transistors (TFTs) of a second conductivity
6251713 Method of making an SRAM storage cell with N channel thin film transistor load devices June 26, 2001
An SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the cell, and a pair of N channel thin film transistors in depletion mode with gate and source shorted to provide load devices for
6147899 Radiation hardened SRAM device having cross-coupled data cells November 14, 2000
A memory cell with increased resistance to high energy particle radiation. When a memory cell is subjected to high energy particles hit, such as may occur in outer space or in certain harsh environments, design is provided that ensures the data will be maintained in its current state. In
6140684 SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along October 31, 2000
A six transistor static random access memory (SRAM) cell with thin-film pull-up transistors and method of making the same includes providing two bulk silicon pull-down transistors of a first conductivity type, two active gated pull-up thin-film transistors (TFTs) of a second conductivity
6034410 MOSFET structure with planar surface March 7, 2000
A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photoresist layer is then formed and
6005296 Layout for SRAM structure December 21, 1999
A layout is provided for an SRAM structure. The layout includes a first storage transistor cross-coupled to a second storage transistor to form an SRAM cell. The source regions of the first and second storage transistors are formed in a common region in the substrate to provide a more co
5939934 Integrated circuit passively biasing transistor effective threshold voltage and related methods August 17, 1999
An integrated circuit preferably includes a plurality of enhancement-mode MOSFETs on a substrate with each MOSFET having an initial threshold voltage, and a plurality of resistors connected to define a resistor voltage divider for passively biasing the MOSFETs to produce an absolute
5929695 Integrated circuit having selective bias of transistors for low voltage and low standby current July 27, 1999
An integrated circuit includes a plurality of MOSFETs on a substrate. The plurality of MOSFETs preferably includes at least one MOSFET having a first conductivity type and at least one MOSFET having a second conductivity type. Each MOSFET has an initial threshold voltage. The integra
5895237 Narrow isolation oxide process April 20, 1999
A high performance CMOS process using grown field oxide for active area isolation takes advantage of process steps used in LDD transistor fabrication to reduce the chip space occupied by the field oxide. Portions of the spacer oxide layer are retained intact over the field oxide during
5889713 Testing of embedded memory by coupling the memory to input/output pads using switches March 30, 1999
A method and circuits for coupling a memory embedded in an integrated circuit to interconnect pads during a memory test mode is disclosed. The integrated circuit contains a processor, an embedded memory and a switching circuit for: (1) temporary coupling the interconnect pads of the
5885871 Method of making EEPROM cell structure March 23, 1999
A memory cell for an EEPROM memory is fabricated to provide increased oxide thickness at the edge of the tunnel oxide and under the edges of the polysilicon capacitor plate in order to improve the dielectric integrity of the capacitor structure. In one embodiment using a silicided po
5883544 Integrated circuit actively biasing the threshold voltage of transistors and related methods March 16, 1999
An integrated circuit includes a plurality of MOSFETs having channels of a first conductivity type, and having active control of an effective threshold voltage of the MOSFETs to be less than an absolute value of an initial threshold voltage. In this embodiment, a first MOSFET has a c
5874769 Mosfet isolation structure with planar surface February 23, 1999
A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photoresist layer is then formed and
5870330 Method of making and structure of SRAM storage cell with N channel thin film transistor load dev February 9, 1999
An SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the cell, and a pair of N channel thin film transistors in depletion mode with gate and source shorted to provide load devices for
5869388 Method of gettering using doped SOG and a planarization technique February 9, 1999
A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate electrode is formed over a substrate having source/drain regions adjacent to the gate electrode and in the substrate. A silicon dioxide layer is
5849614 Method of isolation by active transistors with grounded gates December 15, 1998
An isolation gate structure is formed between active areas on a P-type semiconductor substrate. The isolation structure includes a thick gate oxide layer over which is formed a P-doped polycrystalline silicon layer. The polycrystalline silicon layer is electrically connected to the s
5841784 Testing and repair of embedded memory November 24, 1998
A method and circuits for coupling a memory embedded in an integrated circuit to interconnect pads during a memory test mode is disclosed. The integrated circuit contains a processor, an embedded memory and a switching circuit for: (1) temporary coupling the memory array and memory p
5834966 Integrated circuit sensing and digitally biasing the threshold voltage of transistors and relate November 10, 1998
An integrated circuit includes a plurality of MOSFETs on a substrate. A plurality of sensing MOSFETs are used to generate a plurality of comparison signals based upon comparing signals related to the sensed initial threshold voltages to respective reference voltages from a spread of
5831326 Semiconductor device with resistive load element November 3, 1998
A method for fabricating a resistive load element for a semiconductor device can be used with standard semiconductor processes. A layer of second level poly is deposited and lightly doped P-type. A resist mask is used to dope selected regions of the poly layer N-type. The poly layer is
5825070 Structure for transistor devices in an SRAM cell October 20, 1998
An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate tran
5821600 Isolation by active transistors with grounded gates October 13, 1998
An isolation gate structure is formed between active areas on a P-type semiconductor substrate. The isolation structure includes a thick gate oxide layer over which is formed a P-doped polycrystalline silicon layer. The polycrystalline silicon layer is electrically connected to the s
5821136 Inverted field-effect device with polycrystalline silicon/germanium channel October 13, 1998
A CMOS device architecture which includes substrate-gated inverted PMOS transistors, as well as bulk NMOS. The inverted-PMOS channels are formed in a different layer from the NMOS gates, and these layers may even have different compositions. Moreover, the NMOS and inverted-PMOS devices h
5801396 Inverted field-effect device with polycrystalline silicon/germanium channel September 1, 1998
A CMOS device architecture which includes substrate-gated inverted PMOS transistors, as well as bulk NMOS. The inverted-PMOS channels are formed in a different layer from the NMOS gates, and these layers may even have different compositions. Moreover, the NMOS and inverted-PMOS devices h
5798278 Method of forming raised source/drain regions in an integrated circuit August 25, 1998
A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A transistor encapsulated in a dielectric is formed over a substrate. First source and drain regions are formed in the substrate adjacen
5795800 Integrated circuit fabrication method with buried oxide isolation August 18, 1998
A CMOS SRAM cell in which a patterned SIMOX layer forms a buried oxide beneath the PMOS devices, but not beneath the NMOS devices. Latchup is impossible, and well diffusions are not needed.
5734602 Virtual ground read only memory circuit March 31, 1998
A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of
5706226 Low voltage CMOS SRAM January 6, 1998
A complementary-metal-oxide-semiconductor, static-random-access-memory cell has two pairs of n-channel and p-channel transistors in complementary symmetry, push-pull arrangement. One pair of complementary transistors stores the binary state of the memory cell, and the other pair of c
5696021 Method of making a field oxide isolation structure December 9, 1997
A method for creating isolation structures in a substrate without having to increase the field implant doses to prevent punch through. This particular advantage is achieved by first growing a pad oxide on the substrate. Polysilicon is deposited on top of the pad oxide layer. Next, silico
5670424 Method for making local interconnect structure September 23, 1997
An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rathe










 
 
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