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Chan; Hsun-Chang
Hsin-Chu, TW
No. of patents:

Patent Number Title Of Patent Date Issued
7528478 Semiconductor devices having post passivation interconnections and a buffer layer May 5, 2009
An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pat
7026233 Method for reducing defects in post passivation interconnect process April 11, 2006
A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer

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