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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Cha; Cher Liang
Address:
Singapore, SG
No. of patents:
22
Patents:












Patent Number Title Of Patent Date Issued
7573081 Method to fabricate horizontal air columns underneath metal inductor August 11, 2009
A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air co
7112866 Method to form a cross network of air gaps within IMD layer September 26, 2006
The invention provides a new multilevel interconnect structure of air gaps in a layer of IMD. A first layer of dielectric is provided over a surface; the surface contains metal points of contact. Trenches are provided in this first layer of dielectric. The trenches are filled with a
7105420 Method to fabricate horizontal air columns underneath metal inductor September 12, 2006
A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air co
6730571 Method to form a cross network of air gaps within IMD layer May 4, 2004
In accordance with the objectives of the invention a new method is provided for creating air gaps in a layer of IMD. First and second layers of dielectric are successively deposited over a surface; the surface contains metal lines running in an Y-direction. Trenches are etched in the fir
6680239 Effective isolation with high aspect ratio shallow trench isolation and oxygen or field implant January 20, 2004
A method for forming shallow trench isolation (STI) with a higher aspect ratio is given. This method allows the formation of narrower and deeper trench isolation regions while avoiding substrate damage due to excessive etching and severe microloading effects. In addition, it yields unifo
6610575 Forming dual gate oxide thickness on vertical transistors by ion implantation August 26, 2003
A method of structures having dual gate oxide thicknesses, comprising the following steps. A substrate having first and second pillars is provided. The first and second pillars each having an outer side wall and an inner side wall. At least one of the outer or inner side walls of at leas
6605501 Method of fabricating CMOS device with dual gate electrode August 12, 2003
A method of fabricating dual gate oxide thicknesses comprising the following steps. A substrate is provided having a first pillar and a second pillar. A gate dielectric layer is formed over the substrate and the first and second pillars. First and second thin spacers are formed over
6566209 Method to form shallow junction transistors while eliminating shorts due to junction spiking May 20, 2003
A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through
6531750 Shallow junction transistors which eliminating shorts due to junction spiking March 11, 2003
A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through
6501122 Flash device having a large planar area ono interpoly dielectric December 31, 2002
A new method of fabricating a stacked gate Flash EEPROM device having an improved interpoly oxide layer is described. A gate oxide layer is provided on the surface of a substrate. A first polysilicon layer is deposited overlying the gate oxide layer and patterned to form a floating g
6483148 Self-aligned elevated transistor November 19, 2002
A method of forming a self-aligned elevated transistor using selective epitaxial growth is described. An oxide layer is provided overlying a semiconductor substrate. The oxide layer is etched through to the semiconductor substrate to form a trench having a lower portion contacting th
6380084 Method to form high performance copper damascene interconnects by de-coupling via and metal line April 30, 2002
A method to form robust dual damascene interconnects by decoupling via and connective line trench filling has been achieved. A first dielectric layer is deposited overlying a silicon nitride layer. A shielding layer is deposited. The shielding layer, the first dielectric layer, and the
6326272 Method for forming self-aligned elevated transistor December 4, 2001
A method of forming a self-aligned elevated transistor using selective epitaxial growth is described. An oxide layer is provided overlying a semiconductor substrate. The oxide layer is etched through to the semiconductor substrate to form a trench having a lower portion contacting th
6303418 Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant October 16, 2001
A method of forming a metal gate structure, on a high k gate insulator layer, for NMOS devices, and simultaneously forming a metal-polysilicon gate structure, on the same high k gate insulator layer, for PMOS devices, has been developed. The method features forming openings in a composit
6297109 Method to form shallow junction transistors while eliminating shorts due to junction spiking October 2, 2001
A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through
6252277 Embedded polysilicon gate MOSFET June 26, 2001
Formation of a MOSFET with a polysilicon gate electrode embedded within a silicon trench is described. The MOSFET retains all the features of conventional MOSFETs with photolithographically patterned polysilicon gate electrodes, including robust LDD (lightly doped drain) regions formed i
6221727 Method to trap air at the silicon substrate for improving the quality factor of RF inductors in April 24, 2001
A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacturing of integrated circuits is described. A field oxide region is formed in and on a semiconductor substrate and then removed whereby a well is left in the semiconductor substrate. A polish
6207534 Method to form narrow and wide shallow trench isolations with different trench depths to elimina March 27, 2001
A method of forming trenches having different depths for use in shallow trench isolations is achieved. Dishing problems due to isolation oxide thinning over wide trenches is eliminated. A silicon substrate is provided. A pad oxide is grown. A polishing stop of silicon nitride is depo
6150232 Formation of low k dielectric November 21, 2000
A method for creating low intra-level dielectric interface between conducting lines using conventional deposition and etching processes. A layer of conducting lines is formed interspersed with dielectric material. A dummy, high-density pattern of low k dielectric material is created on
6140197 Method of making spiral-type RF inductors having a high quality factor (Q) October 31, 2000
A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacture of integrated circuits is described. A metal line is provided overlying a dielectric layer on a semiconductor substrate. An intermetal dielectric layer is deposited overlying the metal l
6096604 Production of reversed flash memory device August 1, 2000
This invention relates to the new reversed flash memory device which has improved electrical performance, yield and reliability because of better control of the dielectric interfaces resulting from first making the poly 2 control gate within the silicon substrate. The reverse structure i
6051467 Method to fabricate a large planar area ONO interpoly dielectric in flash device April 18, 2000
A new method of fabricating a stacked gate Flash EEPROM device having an improved interpoly oxide layer is described. A gate oxide layer is provided on the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate oxide layer. The first polysilicon










 
 
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