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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Cederbaum; Carl
Address:
Paris, FR
No. of patents:
4
Patents:




Patent Number Title Of Patent Date Issued
5381046 Stacked conductive resistive polysilicon lands in multilevel semiconductor chips January 10, 1995
A semiconductor structure for making four device SRAMs with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology. The structure is formed from a semiconductor substrate with active regions of devices therein and polysilicon lines formed thereupon. A first thick
5275963 Method of forming stacked conductive and/or resistive polysilicon lands in multilevel semiconduc January 4, 1994
A semiconductor structure including: a semiconductor substrate (18/19) having active regions (21) of devices (T1, . . . ) therein and/or polysilicon lines (23-1, . . .) formedthereupon; a first thick passivating layer (26/27) formed above the substrate having a set of first metal contact
5112765 Method of forming stacked tungsten gate PFET devices and structures resulting therefrom May 12, 1992
A manufacturing method is provided for producing a stacked semiconductor structure including: depositing a first thick passivating layer onto the base structure; forming first stud openings in the first thick passivating layer exposing at least one active region and/or one of the polysil
5100817 Method of forming stacked self-aligned polysilicon PFET devices and structures resulting therefr March 31, 1992
A stacked semiconductor structure including a base structure (18/19) is comprised of a semiconductor substrate having active regions (21) of devices (N1, . . . ) formed therein and/or a plurality of polysilicon lines (23-1, . . . ) formed thereupon; a first thick passivating layer (2


 
 
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