| Patent Number |
Title Of Patent |
Date Issued |
| RE38685 |
Data-output driver circuit and method |
January 11, 2005 |
| A drive circuit includes drive input and output terminals, a supply terminal, a drive transistor, and a drive-control circuit. The drive transistor includes a control terminal, a first transistor terminal coupled to the drive output terminal, and a second transistor terminal coupled |
| RE36821 |
Wordline driver circuit having a directly gated pull-down device |
August 15, 2000 |
| The invention is a circuit and method for quickly driving non-selected wordlines to correct potentials. The invention drives the non-selected wordlines to low potentials through a driving device directly gated by a primary select predecode signal generated by decode circuitry. The drivin |
| RE35764 |
Inverting output driver circuit for reducing electron injection into the substrate |
April 7, 1998 |
| A new inverting output driver circuit is disclosed that reduces electron injection into the substrate by the drain of the circuit's pull-up field effect transistor. This is accomplished by adding additional circuitry that allows the gate voltage of the pull-up transistor to track the sou |
| RE35750 |
Wordline driver circuit having an automatic precharge circuit |
March 24, 1998 |
| The invention is an automatic precharge circuit featuring precharge devices each of which is interposed between a high voltage node, connectable to a supply potential, and a serial node. The precharge devices are gated automatically by a primary predecode signal of a decode portion of th |
| 7567477 |
Bias sensing in sense amplifiers through a voltage-coupling/decoupling device |
July 28, 2009 |
| Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplif |
| 7408828 |
System and method for reducing power consumption during extended refresh periods of dynamic rand |
August 5, 2008 |
| A dynamic random access memory ("DRAM") device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage of one-half the supply voltage to the cell plate of a DRAM array in a normal refresh mode |
| 7082073 |
System and method for reducing power consumption during extended refresh periods of dynamic rand |
July 25, 2006 |
| A dynamic random access memory ("DRAM") device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage of one-half the supply voltage to the cell plate of a DRAM array in a normal refresh mode |
| 7072235 |
Bias sensing in DRAM sense amplifiers through coupling and decoupling device |
July 4, 2006 |
| Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplif |
| 6954385 |
Method and apparatus for sensing resistive memory state |
October 11, 2005 |
| A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit c |
| 6922368 |
Apparatus and structure for rapid enablement |
July 26, 2005 |
| A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time del |
| 6791885 |
Programmable conductor random access memory and method for sensing same |
September 14, 2004 |
| A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit c |
| 6778453 |
METHOD OF STORING A TEMPERATURE THRESHOLD IN AN INTEGRATED CIRCUIT, METHOD OF MODIFYING OPERATIO |
August 17, 2004 |
| A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing p |
| 6760264 |
Apparatus and structure for rapid enablement |
July 6, 2004 |
| A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time del |
| 6757202 |
Bias sensing in DRAM sense amplifiers |
June 29, 2004 |
| Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplif |
| 6714468 |
Circuit and method for testing a memory device |
March 30, 2004 |
| A voltage generator coupled to a capacitor is provided. In one embodiment, the voltage generator includes an input that receives a control signal that indicates a desired current level output, and further includes circuitry adapted to generate a selected voltage, activate a first current |
| 6686796 |
Temperature compensated reference voltage circuit |
February 3, 2004 |
| An integrated circuit voltage regulator compensates for temperature variations by adjusting a gain of an amplifier. In one embodiment, the gain is controlled by a voltage divider circuit comprised of a first resistor having a first temperature coefficient, and a second resistor havin |
| 6633506 |
Antifuse detection circuit |
October 14, 2003 |
| An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The ci |
| 6625080 |
Antifuse detection circuit |
September 23, 2003 |
| An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The ci |
| 6587978 |
Circuit and method for varying a pulse width of an internal control signal during a test mode |
July 1, 2003 |
| The invention is a dynamic random access memory (DRAM) device having an electronic test key fabricated on board and is a method for testing the DRAM. The electronic test key generates a signal which effects a variation in a pulse width of an internal control signal to stress the DRAM dur |
| 6587892 |
Method of reducing data communication time |
July 1, 2003 |
| A memory device is described which is fabricated as an integrated circuit and uses distributed bond pads for electrical connection to an external conductive lead. The distributed bond pads are attached to a external lead, thereby eliminating bus lines on the integrated circuit memory. |
| 6586290 |
Structure for ESD protection in semiconductor chips |
July 1, 2003 |
| An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal |
| 6569727 |
Method of making a single-deposition-layer-metal dynamic random access memory |
May 27, 2003 |
| A 16 megabit (2.sup.24) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little o |
| 6552945 |
METHOD FOR STORING A TEMPERATURE THRESHOLD IN AN INTEGRATED CIRCUIT, METHOD FOR STORING A TEMPER |
April 22, 2003 |
| A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing p |
| 6515885 |
Tri-stating address input circuit |
February 4, 2003 |
| An address buffer for a memory device comprises a tri-state input stage, an address output latch, and an inverter that are successively coupled. In one embodiment, the address buffer uses address enable signals for controlling both the tri-state input stage and the address output latch. |
| 6512412 |
Temperature compensated reference voltage circuit |
January 28, 2003 |
| An integrated circuit voltage regulator compensates for temperature variations by adjusting a gain of an amplifier. In one embodiment, the gain is controlled by a voltage divider circuit comprised of a first resistor having a first temperature coefficient, and a second resistor havin |
| 6507074 |
Structure for ESD protection in semiconductor chips |
January 14, 2003 |
| An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal condu |
| 6475851 |
Circuit for providing isolation of integrated circuit active areas |
November 5, 2002 |
| Adjacent unassociated field-effect transistors are formed from a single continuous layer of uniformly doped material in a semiconductor substrate. An insulating layer is formed over the active layer. A number of gates in a conductive layer define the transistors. Forming a connection bet |
| 6445610 |
Variable voltage isolation gate and method |
September 3, 2002 |
| A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage pumped higher than the supply voltage during read time to ensure that a |
| 6438645 |
Apparatus and structure for rapid enablement |
August 20, 2002 |
| A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time del |
| 6430095 |
Method for cell margin testing a dynamic cell plate sensing memory architecture |
August 6, 2002 |
| A cell margin test method for a dynamic cell plate sensing (DCPS) memory array. In a DCPS memory array, voltage moves on both a digitline and a cell plate line associated with an accessed memory cell. Voltage movement on the digitline and its associated cell plate line is in opposite |
| 6388314 |
Single deposition layer metal dynamic random access memory |
May 14, 2002 |
| A 16 megabit (2.sup.24) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little o |
| 6385098 |
Method and apparatus for supplying regulated power to memory device components |
May 7, 2002 |
| An internal voltage regulator for a synchronous random access memory ("SDRAM") uses a regulator circuit to supply power to charge pumps that is separate from a regulator circuit that supplies power to the arrays of the SDRAM. The regulator supplies an output voltage to the charge pumps t |
| 6359817 |
Circuit and method for testing a memory device |
March 19, 2002 |
| A method for testing a memory device. The method writes test data to an array of cells of the memory device during a test mode. The method calls for driving a cell plate of the memory device during at least a portion of the test with a current level that is less than the current used dur |
| 6359463 |
Method and apparatus for reducing induced switching transients |
March 19, 2002 |
| An attenuating circuit for reducing the inductively induced voltage transients in an electrical signal. The attenuating circuit is formed by a primary circuit and a smoothing circuit both coupled to a voltage source through an inductive conductor. The primary circuit operates in two stat |
| 6359462 |
Method and apparatus for reducing induced switching transients |
March 19, 2002 |
| An attenuating circuit for reducing the inductively induced voltage transients in an electrical signal. The attenuating circuit is formed by a primary circuit and a smoothing circuit both coupled to a voltage source through an inductive conductor. The primary circuit operates in two stat |
| 6345012 |
Tri-stating address input circuit |
February 5, 2002 |
| An address buffer for a memory device comprises a tri-state input stage, an address output latch, and an inverter that are successively coupled. In one embodiment, the address buffer uses address enable signals for controlling both the tri-state input stage and the address output latch. |
| 6327200 |
Circuit and method for testing a memory device |
December 4, 2001 |
| A method for testing a memory device. The method writes test data to an array of cells of the memory device during a test mode. The method calls for driving a cell plate of the memory device during at least a portion of the test with a current level that is less than the current used dur |
| 6320817 |
Tri-stating address input circuit |
November 20, 2001 |
| An address buffer for a memory device comprises a tri-state input stage, an address output latch, and an inverter that are successively coupled. In one embodiment, the address buffer uses address enable signals for controlling both the tri-state input stage and the address output latch. |
| 6275409 |
Methods of operating a dynamic random access memory |
August 14, 2001 |
| A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage pumped higher than the supply voltage during read time to ensure that a |
| 6274928 |
Single deposition layer metal dynamic random access memory |
August 14, 2001 |
| A 16 megabit (2.sup.24) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little o |
| 6242782 |
Circuit for providing isolation of integrated circuit active areas |
June 5, 2001 |
| The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that |
| 6233190 |
Method of storing a temperature threshold in an integrated circuit, method of modifying operatio |
May 15, 2001 |
| A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing p |
| 6233179 |
Circuit and method for reading and writing data in a memory device |
May 15, 2001 |
| A memory device. The memory device includes an array of memory cells that are coupled to a number of word lines and a number of digit lines. The memory device further includes an addressing circuit that is coupled to the array. The addressing circuit selects a memory cell based on a |
| 6229333 |
Apparatus for reducing induced switching transients |
May 8, 2001 |
| An attenuating circuit for reducing the inductively induced voltage transients in an electrical signal. The attenuating circuit is formed by a primary circuit and a smoothing circuit both coupled to a voltage source through an inductive conductor. The primary circuit operates in two stat |
| 6219293 |
Method and apparatus for supplying regulated power to memory device components |
April 17, 2001 |
| An internal voltage regulator for a synchronous random access memory "SDRAM") uses a regulator circuit to supply power to charge pumps that is separate from a regulator circuit that supplies power to the arrays of the SDRAM. The regulator supplies an output voltage to the charge pumps th |
| 6184067 |
Memory device with multiple input/output connections |
February 6, 2001 |
| A memory device is described which is fabricated as an integrated circuit and uses distributed bond pads for electrical connection to an external conductive lead. The distributed bond pads are attached to a external lead, thereby eliminating bus lines on the integrated circuit memory. |
| 6181627 |
Antifuse detection circuit |
January 30, 2001 |
| An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The ci |
| 6154401 |
Circuit and method for memory device with defect current isolation |
November 28, 2000 |
| A memory device. The memory device includes an array of word lines and complementary bit line pairs. A number of memory cells are each addressably coupled to intersections of the word line with a bit line of a complementary bit line pair. The memory device also includes addressing ci |
| 6154056 |
Tri-stating address input circuit |
November 28, 2000 |
| An address buffer for a memory device comprises a tri-state input stage, an address output latch, and an inverter that are successively coupled. In one embodiment, the address buffer uses address enable signals for controlling both the tri-state input stage and the address output latch. |
| 6141270 |
Method for cell margin testing a dynamic cell plate sensing memory architecture |
October 31, 2000 |
| A cell margin test method for a dynamic cell plate sensing (DCPS) memory array. In a DCPS memory array, voltage moves on both a digitline and a cell plate line associated with an accessed memory cell. Voltage movement on the digitline and its associated cell plate line is in opposite |
