| Patent Number |
Title Of Patent |
Date Issued |
| 7592849 |
Level shifter for semiconductor memory device implemented with low-voltage transistors |
September 22, 2009 |
| A level shifter is proposed. The level shifter includes a stage having a first branch and a second branch, each branch including: a selection terminal for receiving a selection signal, the selection signal received by the first branch and the second branch being alternatively at a first |
| 7184319 |
Method for erasing non-volatile memory cells and corresponding memory device |
February 27, 2007 |
| The invention relates to a method for erasing non-volatile memory cells, and to a corresponding non-volatile memory device of the programmable and electrically erasable type implementing the method, and comprising a memory cell array organized in a row-and-column layout, and divided in |
| 7168016 |
Method and a device for testing electronic memory devices |
January 23, 2007 |
| A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test |
| 7035142 |
Non volatile memory device including a predetermined number of sectors |
April 25, 2006 |
| The device includes a circuit for sector remapping having a CAM (Content Addressable Memory) unit, associated to and in data communication with a multiplexer unit. The CAM unit detects that a sector is defective, it provides the pre-programmed address of a replacing sector and it act |
| 7027317 |
Semiconductor memory with embedded DRAM |
April 11, 2006 |
| A semiconductor memory comprises a plurality of memory cells, for example Flash memory cells, arranged in a plurality of lines, and a plurality of memory cell access signal lines, each one associated with at least one respective line of memory cells, for accessing the memory cells of the |
| 6947329 |
Method for detecting a resistive path or a predetermined potential in non-volatile memory electr |
September 20, 2005 |
| The invention relates to a method for pinpointing erase-failed memory cells and to a relevant integrated non-volatile memory device, of the programmable and electrically erasable type comprising a sectored array of memory cells arranged in rows and columns, with at least one row-decoding |
| 6944061 |
Single cell erasing method for recovering memory cells under programming disturbs in non volatil |
September 13, 2005 |
| The present invention relates to a particular single cell erasing method for recovering memory cells under reading or programming disturbs in non volatile semiconductor memory electronic devices comprising cell matrix split in sectors and organized in rows, or word lines, and columns, or |
| 6891755 |
Architecture for a flash-EEPROM simultaneously readable in other sectors while erasing and/or pr |
May 10, 2005 |
| A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sec |
| 6871258 |
METHOD FOR ERASING AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-F |
March 22, 2005 |
| Described herein is an erase method for an electrically erasable nonvolatile memory device, in particular an EEPROM-FLASH nonvolatile memory device, comprising a memory array formed by a plurality of memory cells arranged in rows and columns and grouped in sectors each formed by a pl |
| 6829168 |
Power supply circuit structure for a row decoder of a multilevel non-volatile memory device |
December 7, 2004 |
| A power supply circuit structure is useful with a row decoder for reading/writing data from/into memory cells of an integrated electrically programmable/erasable non-volatile memory device incorporating an array of multilevel memory cells. Advantageously, multiple supply voltages to the |
| 6728141 |
Method and circuit for timing dynamic reading of a memory cell with control of the integration t |
April 27, 2004 |
| The method for timing reading of a memory cell envisages supplying the memory cell (with a constant current by means of a first capacitive element, integrating said current in a time interval, and controlling the duration of the time interval in such a way as to compensate for any de |
| 6724658 |
Method and circuit for generating reference voltages for reading a multilevel memory cell |
April 20, 2004 |
| The circuit for generating reference voltages for reading a multilevel memory cell includes the following: a first memory cell and a second memory cell respectively having a first reference programming level and a second reference programming level; a first reference circuit and a second |
| 6646913 |
Method for storing and reading data in a multilevel nonvolatile memory |
November 11, 2003 |
| The data management method applies to a multilevel nonvolatile memory device having a memory array formed by a plurality of memory cells. Each of the memory cells stores a number of bits that is not an integer power of two, for example three. In this way, one data byte is stored in a |
| 6643179 |
Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile |
November 4, 2003 |
| The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell by a capacitive element. The capacitive element is initially charged and then discharged linearly in a preset time, while the memory cell is biased at a constant voltage. In |
| 6639833 |
Method and circuit for dynamic reading of a memory cell at low supply voltage and with low outpu |
October 28, 2003 |
| The method for reading a memory cell includes supplying the cell with a first charge quantity through a capacitive integration element and reintegrating the first charge quantity through a plurality of second charge quantities supplied alternately and in succession to the capacitive |
| 6587914 |
Non-volatile memory capable of autonomously executing a program |
July 1, 2003 |
| A non-volatile semiconductor memory device that includes an address buffer block, a matrix of memory cells, and an output buffer block. The address buffer block receives input signals external to the memory device, that in a first operating mode are controlled by devices outside to the m |
| 6532171 |
Nonvolatile semiconductor memory capable of selectively erasing a plurality of elemental memory |
March 11, 2003 |
| A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective |
| 6515911 |
Circuit structure for providing a hierarchical decoding in semiconductor memory devices |
February 4, 2003 |
| A circuit device structured to enable a hierarchic form of row decoding in semiconductor memory devices of the non-volatile type and including a matrix of memory cells with sectors organized into columns, wherein each sector has a group of local word lines individually connected to a mai |
| 6493260 |
Nonvolatile memory device, having parts with different access time, reliability, and capacity |
December 10, 2002 |
| The multilevel memory device has a memory section containing cells that can be programmed with a predetermined number of levels greater than two, i.e., a multilevel array, and a memory section containing cells that can be programmed with two levels, i.e., a bilevel array. The multilevel |
| 6456530 |
Nonvolatile memory device with hierarchical sector decoding |
September 24, 2002 |
| The memory device has hierarchical sector decoding. A plurality of groups of supply lines is provided, one for each sector row, extending parallel to the sector rows. A plurality of switching stages are each connected between a respective sector and a respective group of supply lines; th |
| 6456527 |
Nonvolatile multilevel memory and reading method thereof |
September 24, 2002 |
| A multilevel memory stores words formed by a plurality of binary subwords in a plurality of cells, each cell having has a respective threshold value. The cells are arranged on cell rows and columns, are grouped into sectors divided into sector blocks, and are selected via a global row |
| 6433583 |
CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolati |
August 13, 2002 |
| The switch circuit receives a first supply voltage and a second supply voltage different from each other; a control input receiving a control signal that may be switched between the first supply voltage and ground; a driving inverter stage supplied by the second supply voltage and defini |
| 6396168 |
Programmable logic arrays |
May 28, 2002 |
| A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be |
| 6356481 |
Row decoder for a nonvolatile memory with capability of selectively biasing word lines to positi |
March 12, 2002 |
| The row decoder includes, for each word line of the memory, a respective biasing circuit receiving at the input a row selection signal switching, in preset operating conditions, between a supply voltage and a ground voltage and supplying at the output a biasing signal for the respective |
| 6351413 |
Nonvolatile memory device, in particular a flash-EEPROM |
February 26, 2002 |
| The memory array comprises a plurality of cells, grouped together in sectors and arranged in sector rows and columns, and has both hierarchical row decoding and hierarchical column decoding. Global word lines are connected to at least two word lines in each sector, through local row |
| 6327184 |
Read circuit for a nonvolatile memory |
December 4, 2001 |
| The read circuit comprises an array branch having an input array node connected, via an array bit line, to an array cell; a reference branch having an input reference node connected, via a reference bit line, to a reference cell; a current-to-voltage converter connected to an output |
| 6304490 |
Memory cell integrated structure with corresponding biasing device |
October 16, 2001 |
| A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a su |
| 6301152 |
Non-volatile memory device with row redundancy |
October 9, 2001 |
| A non-volatile memory device is organized with memory cells that are arranged by row and by column. The memory device includes a sector of matrix cells, row decoders and column decoders suitable to decode address signals and to activate respectively the rows or said columns, at least a |
| 6301149 |
Method for reading a multilevel nonvolatile memory and multilevel nonvolatile memory |
October 9, 2001 |
| The sensing circuits comparing the current flowing in the cell with a plurality of reference currents are not identical to each other but differently amplify the compared currents. In particular, the sensing circuit associated with the lowest reference current amplifies the cell curr |
| 6286086 |
Data protection method for a semiconductor memory and corresponding protected memory device |
September 4, 2001 |
| A method of protecting data in a semiconductor electronic memory, which includes using a protected memory portion within the matrix and respective dedicated decoding portions for storing, into the protected portion, a protection code without the address area of the matrix. The protection |
| 6266222 |
ESD protection network for circuit structures formed in a semiconductor |
July 24, 2001 |
| An ESD protection network protects a CMOS circuit structure integrated in a semiconductor substrate. The circuit structure includes discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one |
| 6237104 |
Method and a related circuit for adjusting the duration of a synchronization signal ATD for timi |
May 22, 2001 |
| A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it |
| 6215329 |
Output stage for a memory device and for low voltage applications |
April 10, 2001 |
| The present invention relates to an output stage for an electronic memory device and for low supply-voltage applications and is the type comprising a final stage of the pull-up/pull-down type made up of a complementary pair of transistors inserted between a primary reference supply volta |
| 6184741 |
Bidirectional charge pump generating either a positive or negative voltage |
February 6, 2001 |
| A charge pump comprises at least one charge pump stage including a first diode having an anode and a cathode, and a capacitor having a first plate connected to the cathode of the diode and a second plate connected to a clock signal that periodically varies between a reference voltage and |
| 6181602 |
Device and method for reading nonvolatile memory cells |
January 30, 2001 |
| A method for reading memory cells that includes supplying simultaneously two memory cells, both storing a respective unknown charge condition; generating two electrical quantities, each correlated to a respective charge condition of the respective memory cell; comparing the two elect |
| 6169423 |
Method and circuit for regulating the length of an ATD pulse signal |
January 2, 2001 |
| The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a |
| 6157225 |
Driving circuit with three output levels, one output level being a boosted level |
December 5, 2000 |
| A driving circuit supplied by a supply voltage and a reference voltage, generates an output signal and comprises a first circuit adapted to selectively couple the output signal to the reference voltage or to an internal voltage line internal to the driving circuit in response to a fi |
| 6151251 |
Memory cell integrated structure with corresponding biasing device |
November 21, 2000 |
| A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a su |
| 6150844 |
High voltage tolerance output stage |
November 21, 2000 |
| An output stage for electronic circuits with high voltage tolerance and of the type comprising an output buffer made up of a complementary transistor pair comprising a P-channel MOS pull-up transistor and an N-channel MOS pull-down transistor. The transistors are connected together to ma |
| 6144589 |
Boosting circuit, particularly for a memory device |
November 7, 2000 |
| A boosting circuit supplied by a first voltage level and a second voltage level, and having an output line capable of taking a third voltage level, the circuit having at least two distinct circuits for generating the third voltage level, the at least two circuits selectively activatable |
| 6128225 |
Method and circuit for reading low-supply-voltage nonvolatile memory cells |
October 3, 2000 |
| The read circuit has an array branch connected to an array cell, and a reference branch connected to a reference cell; the array branch presents an array load transistor interposed between a supply line and the array cell, and the reference branch presents a reference load transistor |
| 6122200 |
Row decoder for a flash-EEPROM memory device with the possibility of selective erasing of a sub- |
September 19, 2000 |
| A row decoder includes a plurality of pre-decoding circuits which, starting from row addresses, generate pre-decoding signals and a plurality of final decoding circuits which, starting from the pre-decoding signals, drive the individual rows of the array of the memory device. Each pre-de |
| 6111809 |
Line decoder for a low supply voltage memory device |
August 29, 2000 |
| A decoder comprises a first line placed at a first reference potential (V.sub.CC); a second line placed at a second reference potential switchable between the first reference potential and at least one programming potential higher than the first reference potential; a voltage elevato |
| 6075750 |
Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory |
June 13, 2000 |
| A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input |
| 6069837 |
Row decoder circuit for an electronic memory device, particularly for low voltage applications |
May 30, 2000 |
| A row decoding circuit for an electronic memory cell device, particularly in low supply voltage applications, is described. The row decoding circuit is adapted to boost, through at least one boost capacitor, a read voltage to be applied to a memory column containing a memory cell to be r |
| 6060753 |
Low noise output buffer for semiconductor electronic circuits |
May 9, 2000 |
| A low-noise output stage for an electronic circuit integrated on a semiconductor substrate is disclosed. The low-noise output stage comprises a complementary CMOS transistor pair including a P-channel pull-up transistor and an N-channel pull-down transistor, connected across a first |
| 6018255 |
Line decoder for memory devices |
January 25, 2000 |
| The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuit |
| 5982666 |
Sense amplifier circuit for semiconductor memory devices |
November 9, 1999 |
| A sense amplifier circuit for a semiconductor memory device comprises first current/voltage conversion means for converting a current of a memory cell to be read into a voltage signal, second current voltage/conversion means for converting a reference current into a reference voltage sig |
| 5949713 |
Nonvolatile memory device having sectors of selectable size and number |
September 7, 1999 |
| A memory array is divided, at the design stage, into a plurality of elementary sectors; depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors of desired size and number; a correlating unit memorizes the corre |
| 5946238 |
Single-cell reference signal generating circuit for reading nonvolatile memory |
August 31, 1999 |
| A nonvolatile memory having a memory array including a plurality of data cells and a read circuit. The read circuit includes a plurality of sense amplifiers, each connected to a respective array branch to be connected to the data cells. The nonvolatile memory also includes a reference |
