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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Byun; Jae-seong
Address:
Suwon-si, KR
No. of patents:
5
Patents:












Patent Number Title Of Patent Date Issued
8097480 Liquid crystal display and method of making the same January 17, 2012
A method of making a liquid crystal display having a display region and a non-display region, the method comprises forming a thin film transistor ("TFT") having a drain electrode on an insulating substrate, forming an inorganic layer and an organic insulating layer sequentially on the TF
7800118 Array substrate with reduced pixel defect, method of manufacturing the same and liquid crystal d September 21, 2010
An array substrate includes a transparent substrate, a switching element, an insulating layer and a pixel electrode. The switching element includes a gate electrode formed on the transparent substrate and connected to a gate line, a channel layer formed on the gate electrode and extended
7781268 Array substrate and display panel August 24, 2010
A manufacturing method for an array substrate, comprising forming a gate metal on a base substrate, patterning the gate metal to form a gate part having a gate electrode, a gate line and a gate pad. Then, a gate insulating layer, an active layer and a data metal are sequentially form
7750987 Substrate for a display device, liquid crystal display device having the same and method of manu July 6, 2010
A substrate for a display device includes an insulating substrate, a data line, an insulating layer and a pixel electrode. The insulating substrate has a switching element. The data line is formed on the insulating substrate to be electrically connected to a first electrode of the sw
7319240 Array substrate with reduced pixel defect, method of manufacturing the same and liquid crystal d January 15, 2008
An array substrate includes a transparent substrate, a switching element, an insulating layer and a pixel electrode. The switching element includes a gate electrode formed on the transparent substrate and connected to a gate line, a channel layer formed on the gate electrode and extended










 
 
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