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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Bybell; Anthony J.
Address:
Carrboro, NC
No. of patents:
10
Patents:












Patent Number Title Of Patent Date Issued
8301992 System and apparatus for error-correcting register files October 30, 2012
A method, system and computer program product for enabling a register file to recover from detection of a parity error. A first register file and a second register file are associated with a parallel file structure. When the parity error is detected, the system determines whether the
8250345 Structure for multi-threaded processing August 21, 2012
A design structure embodied in a machine readable storage medium designing, manufacturing, and/or testing a design that includes a multi-threaded processor that executes an instruction of a process of an executing program is provided. The multi-threaded processor includes at least a
8245016 Multi-threaded processing August 14, 2012
A system includes a multi-threaded processor that executes an instruction of a process of an executing program. The multi-threaded processor includes at least a first and a second thread. First and second sets of source registers are respectively allocated to the first and second thr
8140831 Routing instructions in a processor March 20, 2012
Disclosed are a method and system for reducing complexity of routing of instructions from an instruction issue queue to appropriate execution pipelines in a superscalar processor. In one or more embodiments, an instruction steering unit of the superscalar processor receives ordered i
8135927 Structure for cache function overloading March 13, 2012
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a system that includes a cache that stores information in a cache line for processing, wherein the cache line in
8095861 Cache function overloading January 10, 2012
A method includes checking a first parameter that indicates whether parity generation and checking for a at least a sub-portion of a cache line is disabled, setting at least one parity bit, corresponding to the sub-portion, in the cache line with a second parameter that indicates an
7558948 Method for providing zero overhead looping using carry chain masking July 7, 2009
A method for reducing overhead on a loop of a plurality of instructions is disclosed. The method includes providing a carry mask, the carry mask having a first value for the loop being performed at least the particular number of times minus one and a second value for at least a last
7444347 Systems, methods and computer products for compression of hierarchical identifiers October 28, 2008
Management of hierarchical identifiers in simulation models and netlists is accomplished using a prefix compressor algorithm running on a general purpose computer processor. Full name compression is accomplished when hierarchy data and remainder data are split off and prefix compressed.
7181661 Method and system for broadcasting data to multiple tap controllers February 20, 2007
A method and system for testing a plurality of cores in an integrated circuit is disclosed. The method and system include providing a plurality of slave controllers a master controller. Each of the plurality of slave controllers is for testing at least one of the plurality of cores. The
6920519 System and method for supporting access to multiple I/O hub nodes in a host bridge July 19, 2005
Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling routing of DMA data to o










 
 
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