| Patent Number |
Title Of Patent |
Date Issued |
| 7432557 |
FinFET device with multiple channels |
October 7, 2008 |
| A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels |
| 7105421 |
Silicon on insulator field effect transistor with heterojunction gate |
September 12, 2006 |
| A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and |
| 7067349 |
Ion path polymers for ion-motion memory |
June 27, 2006 |
| Methods and systems for improving at least one of carrier ion/charge mobility, distribution and permeability in a semiconducting polymer layer of a microelectronic device are disclosed. The methods include forming a semiconducting polymer layer containing at least one semiconducting |
| 7029958 |
Self aligned damascene gate |
April 18, 2006 |
| A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose |
| 6992004 |
Implanted barrier layer to improve line reliability and method of forming same |
January 31, 2006 |
| A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided |
| 6979642 |
Method of self-annealing conductive lines that separates grain size effects from alloy mobility |
December 27, 2005 |
| A method of forming a conductive structure such as a copper conductive structure, line, or via is optimized for large grain growth and distribution of alloy elements. The alloy elements can reduce electromigration problems associated with the conductive structure. The conductive stru |
| 6977389 |
Planar polymer memory device |
December 20, 2005 |
| The present invention provides a planar polymer memory device that can operate as a non-volatile memory device. A planar polymer memory device can be formed with two or more electrodes and an electrode extension associated with one electrode, wherein a selectively conductive medium and |
| 6916696 |
Method for manufacturing a memory element |
July 12, 2005 |
| A method for manufacturing the memory device by plasma decomposition of sulfur dioxide. A first copper electrode having a surface is provided. The surface of the first copper electrode may be made amorphous. A copper sulfide layer, Cu.sub.x S, where 1.ltoreq.x.ltoreq.2, is disposed on th |
| 6893895 |
CuS formation by anodic sulfide passivation of copper surface |
May 17, 2005 |
| Disclosed are methods of making memory cells and semiconductor devices containing the memory cells. The methods involve passivating a portion of a copper containing electrode to form a copper sulfide layer in an electrochemical cell by applying a current through a passivation solution |
| 6872644 |
Semiconductor device with non-compounded contacts, and method of making |
March 29, 2005 |
| A semiconductor device includes source and drain contact regions which include a non-compounded combination of a semiconductor material and at least one metal. The metal may include an elemental metal, such as gold or aluminum, or may include an intermetallic. The contact regions may be |
| 6861349 |
Method of forming an adhesion layer with an element reactive with a barrier layer |
March 1, 2005 |
| A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a |
| 6852586 |
Self assembly of conducting polymer for formation of polymer memory cell |
February 8, 2005 |
| The present invention provides a selectively conductive organic semiconductor (e.g., polymer) device that can be utilized as a memory cell. A polymer solution including a conducting polymer self assembles relative to a conductive electrode. The process affords self-assembly such that |
| 6835655 |
Method of implanting copper barrier material to improve electrical performance |
December 28, 2004 |
| A method of implanting copper barrier material to improve electrical performance in an integrated circuit fabrication process can include providing a copper layer over an integrated circuit substrate, providing a barrier material at a bottom and sides of a via positioned over the copper |
| 6815340 |
Method of forming an electroless nucleation layer on a via bottom |
November 9, 2004 |
| A method of fabricating an integrated circuit can include performing a reactive ion etch (RIE) to form a via aperture in a dielectric layer where the via aperture exposes a portion of a conductive layer located under the dielectric layer, removing polymer residue from the RIE, and formin |
| 6803267 |
Silicon containing material for patterning polymeric memory element |
October 12, 2004 |
| The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, a |
| 6787458 |
Polymer memory device formed in via opening |
September 7, 2004 |
| One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, form |
| 6787436 |
Silicide-silicon contacts for reduction of MOSFET source-drain resistances |
September 7, 2004 |
| Methods for reducing the contact resistance presented by the interface between a silicide and a doped silicon region are presented. In a first method, a silicide layer and a doped silicon region form an interface. Either a damage-only species or a heavy, metal is implanted through the |
| 6784506 |
Silicide process using high K-dielectrics |
August 31, 2004 |
| A method for preventing the thermal decomposition of a high-K dielectric layer of a gate electrode during the formation of a metal silicide on the gate electrode by using nickel as the metal component of the silicide. |
| 6770905 |
Implantation for the formation of CuX layer in an organic memory device |
August 3, 2004 |
| An organic memory cell having a CuX layer made by implantation is disclosed. The organic memory cell is made of two electrodes, at least one containing copper, with a controllably conductive media between the two electrodes. The controllably conductive media contains an organic semic |
| 6765303 |
FinFET-based SRAM cell |
July 20, 2004 |
| A SRAM cell includes a single FinFET and two resonant tunnel diodes. The FinFet has multiple channel regions formed from separate fins. The resonant tunnel diodes may be formed from FinFET type fins. In particular, the resonant diodes may includes a thin, undoped silicon region surrounde |
| 6764912 |
Passivation of nitride spacer |
July 20, 2004 |
| The formation of metal silicides in silicon nitride spacers on a gate electrode causes bridging between a gate electrode and the source and drain regions of a semiconductor device. The bridging is prevented by forming a thin layer of silicon oxide on the silicon nitride spacers prior |
| 6759308 |
Silicon on insulator field effect transistor with heterojunction gate |
July 6, 2004 |
| A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and |
| 6753247 |
Method(s) facilitating formation of memory cell(s) and patterned conductive |
June 22, 2004 |
| A methodology for forming a memory cell is disclosed, wherein an organic polymer layer is formed over a conductive layer and an electrode layer is formed over the organic polymer layer. A first via is etched into the electrode and organic polymer layers, and a dielectric material is appl |
| 6724087 |
Laminated conductive lines and methods of forming the same |
April 20, 2004 |
| A method of fabricating an integrated circuit can include forming a laminated conductive line. The laminated conductive line can be formed in a dielectric trench. The laminated conductive line can include alternating barrier layers and copper layers. An integrated circuit includes at lea |
| 6716686 |
Method for forming channels in a finfet device |
April 6, 2004 |
| A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels |
| 6710452 |
Coherent diffusion barriers for integrated circuit interconnects |
March 23, 2004 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a bar |
| 6709982 |
Double spacer FinFET formation |
March 23, 2004 |
| A method for forming a group of structures in a semiconductor device includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, and forming an oxide layer over the conductive layer. The method further includes etching at least one openi |
| 6703308 |
Method of inserting alloy elements to reduce copper diffusion and bulk diffusion |
March 9, 2004 |
| A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a |
| 6703307 |
Method of implantation after copper seed deposition |
March 9, 2004 |
| A method of fabricating an integrated circuit can include forming a barrier layer along lateral side walls and a bottom of a via aperture, forming a seed layer proximate and conformal to the barrier layer, and forming an implanted layer proximate and conformal to the barrier layer and th |
| 6667552 |
Low dielectric metal silicide lined interconnection system |
December 23, 2003 |
| Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and depositing a metal silicide to line the interconnection system. Embodiments include a s |
| 6645797 |
Method for forming fins in a FinFET device using sacrificial carbon layer |
November 11, 2003 |
| A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The meth |
| 6642590 |
Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of mak |
November 4, 2003 |
| A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. A barrier layer is deposite |
| 6624476 |
Semiconductor-on-insulator (SOI) substrate having selective dopant implant in insulator layer an |
September 23, 2003 |
| A semiconductor-on-insulator (SOI) device includes a buried insulator layer and an overlying semiconductor layer. Portions of the insulator layer are doped with the same dopant material, for example boron, as is in corresponding portions of the overlying surface semiconductor layer. A |
| 6613643 |
Structure, and a method of realizing, for efficient heat removal on SOI |
September 2, 2003 |
| In one embodiment, the present invention relates to a method of forming a silicon-on-insulator substrate, involving the steps of providing a first silicon substrate and a second silicon substrate; surface modifying at least one of the first silicon substrate and the second silicon substr |
| 6605513 |
Method of forming nickel silicide using a one-step rapid thermal anneal process and backend proc |
August 12, 2003 |
| A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel |
| 6589866 |
Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method |
July 8, 2003 |
| A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. The metal is then formed on |
| 6583012 |
Semiconductor devices utilizing differently composed metal-based in-laid gate electrodes |
June 24, 2003 |
| MOS transistor and CMOS devices comprising a plurality of transistors including in-laid, metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal filling openings in an insulative layer at the bottom of whi |
| 6562718 |
Process for forming fully silicided gates |
May 13, 2003 |
| A method of forming a fully silicidized gate of a semiconductor device includes forming silicide in active regions and a portion of a gate. A shield layer is blanket deposited over the device. The top surface of the gate electrode is then exposed. A refractory metal layer is deposited an |
| 6559051 |
Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors |
May 6, 2003 |
| High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal |
| 6552395 |
Higher thermal conductivity glass for SOI heat removal |
April 22, 2003 |
| In one embodiment, the present invention relates to a method of forming a silicon-on-insulator substrate, involving the steps of providing a first silicon substrate; forming a beryllium oxide layer over the first silicon substrate, the beryllium oxide layer having one of a first thicknes |
| 6544872 |
Dopant implantation processing for improved source/drain interface with metal silicides |
April 8, 2003 |
| Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or CMOS devices is avoided, or at least substantially reduced, by increasing the dopant implantat |
| 6534822 |
Silicon on insulator field effect transistor with a double Schottky gate structure |
March 18, 2003 |
| A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with an impurity to increase free carrier conductivity. The source region and the drain region are |
| 6534379 |
Linerless shallow trench isolation method |
March 18, 2003 |
| A method of making a semiconductor device and a method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon |
| 6528362 |
Metal gate with CVD amorphous silicon layer for CMOS devices and method of making with a replace |
March 4, 2003 |
| A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the C |
| 6518167 |
Method of forming a metal or metal nitride interface layer between silicon nitride and copper |
February 11, 2003 |
| A method of forming a metal or metal nitride layer interface between a copper layer and a silicon nitride layer can include providing a metal organic gas or metal/metal nitride precursor over a copper layer, forming a metal or metal nitride layer from reactions between the metal organic |
| 6518154 |
Method of forming semiconductor devices with differently composed metal-based gate electrodes |
February 11, 2003 |
| MOS transistors and CMOS devices comprising a plurality of transistors including metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal on a thin gate insulator layer extending over first and second activ |
| 6518113 |
Doping of thin amorphous silicon work function control layers of MOS gate electrodes |
February 11, 2003 |
| Work function control layers are provided in in-laid, metal gate electrode, Si-based MOS transistors and CMOS devices by a process which avoids deleterious dopant implantation processing resulting in damage to the thin gate insulator layer and undesirable doping of the underlying channel |
| 6495887 |
Argon implantation after silicidation for improved floating-body effects |
December 17, 2002 |
| A method of forming a MOSFET device is provided including the steps of forming N.sup.- lightly doped source and drain extension regions in the top silicon layer, forming spacers above the N.sup.- lightly doped source and drain extension regions and forming N.sup.+ source and N.sup.+ drai |
| 6492249 |
High-K gate dielectric process with process with self aligned damascene contact to damascene gat |
December 10, 2002 |
| A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be utilized. P-MOS and N-MOS tran |
| 6486062 |
Selective deposition of amorphous silicon for formation of nickel silicide with smooth interface |
November 26, 2002 |
| A nickel silicide layer is formed on a semiconductor device having a crystalline silicon source/drain region doped with arsenic. Arsenic is doped into the crystalline silicon, by implantation, for example, so that the concentration of arsenic is slightly below the surface of the silicon. |
