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Inventor:
Bueti; Serafino
Address:
Waterbury, VT
No. of patents:
19
Patents:












Patent Number Title Of Patent Date Issued
8291357 On-chip identification circuit incorporating pairs of conductors, each having an essentially ran October 16, 2012
Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip
8234104 Simulation of digital circuits July 31, 2012
A method for simulating a circuit. The method includes, in response to a first mode change triggering event at a first time point and in response to a first data transfer triggering event at a second time point after the first time point, generating a random value of at least a first
8132136 Dynamic critical path detector for digital logic circuit paths March 6, 2012
Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further include
8016482 Method and systems of powering on integrated circuit September 13, 2011
Method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a p
7941772 Dynamic critical path detector for digital logic circuit paths May 10, 2011
Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further include
7865789 System and method for system-on-chip interconnect verification January 4, 2011
A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator
7823107 Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical October 26, 2010
An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted s
7823017 Structure for task based debugger (transaction-event-job-trigger) October 26, 2010
Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structu
7716007 Design structures of powering on integrated circuit May 11, 2010
Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating elemen
7643591 Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical January 5, 2010
A method for noise comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary
7594140 Task based debugger (transaction-event-job-trigger) September 22, 2009
The embodiments of the invention provide an apparatus, method, etc. for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an
7519941 Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for April 14, 2009
Disclosed are embodiments of a manufacturing method that establishes a library of pre-made and pre-qualified masks for patterning different blocks of circuitry that meet established performance and timing requirements. The embodiments of the method use stepped exposures of multiple m
7511548 Clock distribution network, structure, and method for providing balanced loading in integrated c March 31, 2009
A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits an
7483806 Design structures, method and systems of powering on integrated circuit January 27, 2009
Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating elemen
7479819 Clock distribution network, structure, and method for providing balanced loading in integrated c January 20, 2009
A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits an
7313738 System and method for system-on-chip interconnect verification December 25, 2007
A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator
7308668 Apparatus and method for implementing an integrated circuit IP core library architecture December 11, 2007
An integrated circuit (IC) architecture includes a library of intellectual property (IP) cores configured to provide a plurality of individual circuit functions. The IP cores arranged in a manner compatible with a customized, functional selection of individual ones of the IP cores, w
7275011 Method and apparatus for monitoring integrated circuit temperature through deterministic path de September 25, 2007
An apparatus for monitoring the temperature of an integrated circuit device includes a conductive wiring pattern formed on the integrated circuit device, extending into areas of the device to be monitored. A deterministic signal source is configured to generate a deterministic signal
7129821 Communication systems and methods using microelectronics power distribution network October 31, 2006
A communication system, which includes a microelectronics chip including a power distribution network; a transmitter operatively configured to generate a communication signal and provide the communication signal to the power distribution network; and a receiver operatively configured to










 
 
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