| Patent Number |
Title Of Patent |
Date Issued |
| 7601575 |
Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor per |
October 13, 2009 |
| The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active d |
| 7572716 |
Semiconductor doping with improved activation |
August 11, 2009 |
| A method is disclosed for doping a target area of a semiconductor substrate, such as a source or drain region of a transistor, with an electronically active dopant (such as an N-type dopant used to create active areas in NMOS devices, or a P-type dopant used to create active areas in |
| 7553718 |
Methods, systems and structures for forming semiconductor structures incorporating high-temperat |
June 30, 2009 |
| A method (100) of forming semiconductor structures (202) including high-temperature processing steps (step 118), incorporates the use of a high-temperature nitride-oxide mask (220) over protected regions (214) of the device (202). The invention has application in many different embod |
| 7514331 |
Method of manufacturing gate sidewalls that avoids recessing |
April 7, 2009 |
| A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spac |
| 7442597 |
Systems and methods that selectively modify liner induced stress |
October 28, 2008 |
| The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the |
| 7429517 |
CMOS transistor using high stress liner layer |
September 30, 2008 |
| A MOS transistor structure comprising a gate dielectric layer (30), a gate electrode (40), and source and drain regions (70) are formed in a semiconductor substrate (10). First second and third dielectric layers (110), (120), and (130) are formed over the MOS transistor structure. The |
| 7402535 |
Method of incorporating stress into a transistor channel by use of a backside layer |
July 22, 2008 |
| The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located be |
| 7341933 |
Method for manufacturing a silicided gate electrode using a buffer layer |
March 11, 2008 |
| The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes providing a capped polysilicon gate electrode (290) over a substrate |
| 7338888 |
Method for manufacturing a semiconductor device having a silicided gate electrode and a method f |
March 4, 2008 |
| The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, includes forming a polysilico |
| 7306995 |
Reduced hydrogen sidewall spacer oxide |
December 11, 2007 |
| An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen con |
| 7253049 |
Method for fabricating dual work function metal gates |
August 7, 2007 |
| A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon |
| 7244654 |
Drive current improvement from recessed SiGe incorporation close to gate |
July 17, 2007 |
| A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed |
| 7226834 |
PMD liner nitride films and fabrication methods for improved NMOS performance |
June 5, 2007 |
| Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in all or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the |
| 7217626 |
Transistor fabrication methods using dual sidewall spacers |
May 15, 2007 |
| Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is implanted. The method (50) further comprises removing all or a portion of |
| 7208380 |
Interface improvement by stress application during oxide growth through use of backside films |
April 24, 2007 |
| The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a stress inducing pattern on a backside of a microelectronics wafer and growing a gate oxide layer on a front side of the micro |
| 7192894 |
High performance CMOS transistors using PMD liner stress |
March 20, 2007 |
| A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting |
| 7173296 |
Reduced hydrogen sidewall spacer oxide |
February 6, 2007 |
| An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen con |
| 7157358 |
Method for using a wet etch to manufacturing a semiconductor device having a silicided gate elec |
January 2, 2007 |
| The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, forming a polysilicon gate electrod |
| 7148143 |
Semiconductor device having a fully silicided gate electrode and method of manufacture therefor |
December 12, 2006 |
| The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) located over a substrate (110), the |
| 7135361 |
Method for fabricating transistor gate structures and gate dielectrics thereof |
November 14, 2006 |
| Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce n |
| 7129127 |
Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation |
October 31, 2006 |
| A method (200) fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes (210) on a semiconductor body and active regions defined within the semiconductor body in PMOS and NMOS regions. A nitride containing cap oxide layer is formed over the grown |
| 7122435 |
Methods, systems and structures for forming improved transistors |
October 17, 2006 |
| A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Amorphous silicon regions are then formed (114) in the recesses. The amorpho |
| 7061058 |
Forming a retrograde well in a transistor to enhance performance of the transistor |
June 13, 2006 |
| A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is impla |
| 7060579 |
Increased drive current by isotropic recess etch |
June 13, 2006 |
| A method (100) of forming a transistor includes forming a gate structure (108) over a semiconductor body and forming recesses (112) using an isotropic etch using the gate structure as an etch mask. The isotropic etch forms a recess in the semiconductor body that extends laterally in |
| 7045431 |
Method for integrating high-k dielectrics in transistor devices |
May 16, 2006 |
| Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e.g., sidewalls) of high-k dielectric layers during fabrication with an encaps |
| 7012028 |
Transistor fabrication methods using reduced width sidewall spacers |
March 14, 2006 |
| Transistor fabrication methods (50) are presented in which shrinkable sidewall spacers (120) are formed (66, 68) along sides of a transistor gate (114), and a source/drain implant is performed (74) after forming the sidewall spacer (120). The sidewall spacer width is then reduced by |
| 6930007 |
Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor per |
August 16, 2005 |
| The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite-cap to alter the active dopan |
| 6927137 |
Forming a retrograde well in a transistor to enhance performance of the transistor |
August 9, 2005 |
| A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is impla |
| 6921703 |
System and method for mitigating oxide growth in a gate dielectric |
July 26, 2005 |
| Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the |
| 6812073 |
Source drain and extension dopant concentration |
November 2, 2004 |
| A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gat |
| 6806149 |
Sidewall processes using alkylsilane precursors for MOS transistor fabrication |
October 19, 2004 |
| A method for using alkylsilane precursors during the sidewall formation process in MOS transistor fabrication processes. Alkylsilane precursors are used to form carbon contain silicon oxide layers (110) and carbon containing silicon nitride layers (120) during the sidewall formation |
| 6743705 |
Transistor with improved source/drain extension dopant concentration |
June 1, 2004 |
| A method (40) of forming an integrated circuit (60) device including a substrate (64). The method including the step of first (42), forming a gate stack (62) in a fixed relationship to the substrate, the gate stack including a gate having sidewalls. The method further includes the step o |
| 6677201 |
Method of fabricating thermal CVD oxynitride and BTBAS nitride sidewall spacer for metal oxide s |
January 13, 2004 |
| A method for using CVD oxynitride and BTBAS nitride during the sidewall formation process in MOS transistor fabrication processes. A silicon oxynitride layer (110) and a silicon nitride layer (120) are used to form sidewalls for MOS transistors. The silicon nitride layer (120) is formed |
