| Patent Number |
Title Of Patent |
Date Issued |
| 6916525 |
Method of using films having optimized optical properties for chemical mechanical polishing endp |
July 12, 2005 |
| A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the ste |
| 6756316 |
Semiconductor pressure transducer structures and methods for making the same |
June 29, 2004 |
| Disclosed is a method for making a semiconductor pressure transducer structure in CMOS integrated circuits. The method includes patterning a first metallization layer that lies over an first oxide layer to produce a first patterned metallization layer that is not in electrical contact wi |
| 6649253 |
Method of using films having optimized optical properties for chemical mechanical polishing endp |
November 18, 2003 |
| A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the ste |
| 6411367 |
Modified optics for imaging of lens limited subresolution features |
June 25, 2002 |
| A system and method is disclosed for enhancing an optical lithography process by capturing light diffracted from a mask having features to be exposed onto a wafer. In one embodiment, a system of the present invention has in place a mask, a wafer and a reduction lens such that the reducti |
| 6399432 |
Process to control poly silicon profiles in a dual doped poly silicon process |
June 4, 2002 |
| For use with sub-micron CMOS technologies, a gate etch process improves control of the etch profile. Gate stacks utilize N-type or P-type doped amorphous or poly silicon to enhance device performance. However, the different etching characteristics of the N-type versus the P-type amor |
| 6387797 |
Method for reducing the capacitance between interconnects by forming voids in dielectric materia |
May 14, 2002 |
| A method of manufacturing semiconductors is provided which avoids metal deposition in voids formed in the dielectric between interconnects. In a preferred embodiment, an etch stop recess portion is provided over the dielectric which encloses the interconnects to prevent via openings from |
| 6372522 |
Use of optimized film stacks for increasing absorption for laser repair of fuse links |
April 16, 2002 |
| A system for repairable interconnect links using laser energy in a semiconductor integrated circuit die. The integrated circuit die is fabricated to include a plurality of interconnect links. At least a first and a second interconnect element are included in the integrated circuit di |
| 6327695 |
Automated design of on-chip capacitive structures for suppressing inductive noise |
December 4, 2001 |
| Disclosed is a network of on-chip capacitive structures for suppressing power supply inductive noise, methods for making, and systems for designing the on-chip capacitive structures. The network includes a plurality of dummy active regions that are dispersed throughout an integrated |
| 6313466 |
Method for determining nitrogen concentration in a film of nitrided oxide material |
November 6, 2001 |
| In a method for determining the nitrogen concentration in a film of nitrided oxide material formed over a semiconductor wafer during fabrication of a semiconductor device an optical property of the film of nitrided oxide material is determined. The determined optical property is used |
| 6303192 |
Process to improve adhesion of PECVD cap layers in integrated circuits |
October 16, 2001 |
| A method for making a multi-layered integrated circuit structure, includes depositing a methyl compound spin on glass layer over a substrate. The spin on glass layer is treated by plasma-deposition to form a SiO.sub.2 skin on the methyl compound spin on glass layer and then treated again |
| 6297557 |
Reliable aluminum interconnect via structures |
October 2, 2001 |
| Disclosed is an aluminum filled via hole for use in a semiconductor interconnect structure. The aluminum filled via hole of the semiconductor interconnect structure includes a first patterned metallization layer lying over a first dielectric layer. A second dielectric layer overlying |
| 6277708 |
Semiconductor structures for suppressing gate oxide plasma charging damage and methods for makin |
August 21, 2001 |
| Disclosed is a semiconductor diode structure, and method for making semiconductor diode structures for suppressing transistor gate oxide plasma charging damage. The semiconductor diode structure includes a shallow trench isolation region that is configured to isolate an active region |
| 6275971 |
Methods and apparatus for design rule checking |
August 14, 2001 |
| Disclosed is a method for checking integrated circuit layout design files. The method includes identifying a via geometry that is laid out on a via mask file. Identifying a metallization geometry that is laid out on a metallization mask file. Shifting the via geometry in a first orientat |
| 6226782 |
Apparatus for automated pillar layout |
May 1, 2001 |
| Disclosed is an apparatus for generating mask data suitable to produce a support pillar mask used in air dielectric interconnect structures. The apparatus includes a mask data scanner configured to select features having an interconnect dimension from a first mask. The features having |
| 6221759 |
Method for forming aligned vias under trenches in a dual damascene process |
April 24, 2001 |
| Disclosed is a method for forming an aligned via under a trench to prevent voiding in a dual damascene process. The trench is formed in an oxide layer that is formed over a first metal layer and the first metal layer is formed over a semiconductor substrate. The method includes forming a |
| 6214734 |
Method of using films having optimized optical properties for chemical mechanical polishing endp |
April 10, 2001 |
| A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the ste |
| 6191481 |
Electromigration impeding composite metallization lines and methods for making the same |
February 20, 2001 |
| Disclosed is a semiconductor integrated circuit device having a plurality of metallization levels of patterned metallization lines that are resistant to electromigration voiding, and methods for making the electromigration void resistant metallization lines. The semiconductor integra |
| 6189136 |
Design level optical proximity correction methods |
February 13, 2001 |
| A method for integrating correction features onto selected design features of an integrated circuit mask. The method includes identifying a minimum dimension in the integrated circuit mask. The minimum dimension is configured to define transistor gate electrode features or any critical |
| 6176983 |
Methods of forming a semiconductor device |
January 23, 2001 |
| The present invention provides methods of forming a semiconductor workpiece. One method of forming a semiconductor device in accordance with the present invention includes: providing a semiconductor workpiece; forming a via within the semiconductor workpiece, the via including plural |
| 6162586 |
Method for substantially preventing footings in chemically amplified deep ultra violet photoresi |
December 19, 2000 |
| Disclosed is a method for making a metallization layered stack over an oxide layer of a semiconductor substrate, and a metallization layered stack that assists in providing superior deep UV photolithography resolution. The method includes forming a bottom titanium nitride layer over |
| 6159844 |
Fabrication of gate and diffusion contacts in self-aligned contact process |
December 12, 2000 |
| Disclosed is a method for fabricating conductive contacts in a dielectric layer that overlies a semiconductor wafer having diffusion regions, shallow trench isolation regions, and gate structures that have a part overlying the shallow trench isolation regions. The method includes for |
| 6156626 |
Electromigration bonding process and system |
December 5, 2000 |
| A process and system for connecting a semiconductor chip to a substrate is provided. The process includes providing the substrate that is configured to receive the semiconductor chip that has a bonding pad. The substrate has a first side that is suited to be connected to the semiconducto |
| 6153531 |
Method for preventing electrochemical erosion of interconnect structures |
November 28, 2000 |
| Disclosed is a method for fabricating reliable interconnect structures on a semiconductor substrate that has at least a first dielectric layer, a first patterned metallization layer, a second dielectric layer over the first patterned metallization layer, and a plurality of tungsten plugs |
| 6143642 |
Programmable semiconductor structures and methods for making the same |
November 7, 2000 |
| Disclosed is a method for making a programmable structure on a semiconductor substrate. The semiconductor structure has a first dielectric layer. The method includes plasma patterning a first metallization layer over the first dielectric layer. Forming a second dielectric layer over |
| 6140221 |
Method for forming vias through porous dielectric material and devices formed thereby |
October 31, 2000 |
| A semiconductor device has a device layer, a conductive structure, such as a conductive line, disposed over the device layer, and a porous dielectric layer disposed over the device layer and the conductive structure. At least one via is formed through the porous dielectric layer to the |
| 6140188 |
Semiconductor device having load device with trench isolation region and fabrication thereof |
October 31, 2000 |
| A small-area, high-resistance load device is fabricated in the same area used for the shallow trench isolation region. In an example embodiment, the load device comprises a series resistor coupled to a poly-silicon diode. In one example application, the load device acts as a pull-up |
| 6133635 |
Process for making self-aligned conductive via structures |
October 17, 2000 |
| Disclosed is a process for making a self-aligning conductive via structure in a semiconductor device. The process includes forming a first interconnect metallization layer over an oxide layer. Forming an etch stop layer over the first interconnect metallization layer. Forming a condu |
| 6133111 |
Method of making photo alignment structure |
October 17, 2000 |
| A photo alignment structure integral with a substrate enables the alignment apparatus to receive a reflected light signature of the surface topography of the alignment structure. As the circuit is constructed, the alignment target may be built in tandem with the process. The alignment st |
| 6129613 |
Semiconductor manufacturing apparatus and method for measuring in-situ pressure across a wafer |
October 10, 2000 |
| A pressure sensing structure for measuring a local pressure on a surface of a wafer and a wafer carrier for communicating with the wafer is disclosed. The pressure sensing structure includes a conductive via extending through the wafer, a pressure transducer electrically connected to a f |
| 6127811 |
Micro-electromechanical system and voltage shifter, method of synchronizing an electronic system |
October 3, 2000 |
| The present invention includes a micro-electromechanical system and voltage shifter, method of synchronizing an electronic system and a micromechanical system of a micro-electromechanical system. According to one aspect, the present invention provides a micro-electromechanical system |
| 6093658 |
Method for making reliable interconnect structures |
July 25, 2000 |
| Disclosed is a method for making reliable interconnect structures on a semiconductor wafer having a first dielectric layer. The method includes plasma patterning a first metallization layer over the first dielectric layer. Forming a second dielectric layer over the first metallization |
| 6080661 |
Methods for fabricating gate and diffusion contacts in self-aligned contact processes |
June 27, 2000 |
| Disclosed are methods for making reliable conductive vias in semiconductor devices that are fabricated over a semiconductor wafer. The semiconductor device includes a plurality of transistor devices having diffusion regions and polysilicon gate electrodes, and an oxide material that cove |
| 6077762 |
Method and apparatus for rapidly discharging plasma etched interconnect structures |
June 20, 2000 |
| Disclosed is a method for making reliable interconnect structures on a semiconductor substrate having a first dielectric layer. The method includes plasma patterning a first metallization layer that lies over the first dielectric layer. Forming a second dielectric layer over the first |
| 6057224 |
Methods for making semiconductor devices having air dielectric interconnect structures |
May 2, 2000 |
| A method of making an integrated circuit interconnect structure having air as the effective dielectric between metallization layers includes the steps of: a) providing an air dielectric formation layer of a sacrificial material over a substrate; b) forming a pillar holes in the air diele |
| 6054378 |
Method for encapsulating a metal via in damascene |
April 25, 2000 |
| Disclosed is a method for encapsulating a via over a first metal layer of a semiconductor substrate in a damascene processing to prevent voiding. The method includes forming an intermetal oxide (IMO) layer over the first metal layer and forming a via in the IMO layer such that the via ex |
| 6046102 |
Moisture barrier gap fill structure and method for making the same |
April 4, 2000 |
| Disclosed is a method for making a passivation coated semiconductor structure. The method includes providing a substrate having a metallization line patterned over the substrate. The metallization line defining at least one interconnect feature having a first thickness, and depositin |
| 6034434 |
Optimized underlayer structures for maintaining chemical mechanical polishing removal rates |
March 7, 2000 |
| A method of forming sharp oxide peaks on the surface of a semiconductor wafer for the purpose of conditioning polishing pads used during a Chemical Mechanical Polishing process is disclosed. In order to create oxide peaks on the surface of a wafer, additional elements are added to a |
| 6030885 |
Hexagonal semiconductor die, semiconductor substrates, and methods of forming a semiconductor di |
February 29, 2000 |
| The present invention provides for a hexagonal semiconductor die, semiconductor substrates and methods of forming a semiconductor die. One embodiment of the present invention provides a method of forming a semiconductor die comprising: providing a semiconductor wafer; forming an arra |
| 6028013 |
Moisture repellant integrated circuit dielectric material combination |
February 22, 2000 |
| A method of making an inter-metal oxide layer over a patterned metallization layer of a substrate, and the resulting structure having the inter-metal oxide layer are provided. The method includes depositing a fluorine doped high density plasma (HDP) oxide layer over the patterned met |
| 6020647 |
Composite metallization structures for improved post bonding reliability |
February 1, 2000 |
| Disclosed is a semiconductor chip and method for making a semiconductor chip having strategically placed composite metallization. The semiconductor chip includes a topmost metallization layer that defines a plurality of patterned features including a plurality of input/output metalli |
| 6020616 |
Automated design of on-chip capacitive structures for suppressing inductive noise |
February 1, 2000 |
| Disclosed is a network of on-chip capacitive structures for suppressing power supply inductive noise, methods for making, and systems for designing the on-chip capacitive structures. The network includes a plurality of dummy active regions that are dispersed throughout an integrated |
| 6013927 |
Semiconductor structures for suppressing gate oxide plasma charging damage and methods for makin |
January 11, 2000 |
| Disclosed is a semiconductor diode structure, and method for making semiconductor diode structures for suppressing transistor gate oxide plasma charging damage. The semiconductor diode structure includes a shallow trench isolation region that is configured to isolate an active region |
| 6013536 |
Apparatus for automated pillar layout and method for implementing same |
January 11, 2000 |
| Disclosed is a method for automating support pillar design in air dielectric interconnect structures. The method includes selecting features having an interconnect dimension from a first mask. Providing an intermediate support pattern defining a pillar spacing. Identifying overlap re |
| 6010939 |
Methods for making shallow trench capacitive structures |
January 4, 2000 |
| Disclosed is a capacitive structure and method for making the capacitive structure for suppressing inductive noise produced by high performance device power supplies. The capacitive structure includes a trench having a bottom surface and respective walls that are integral with the bottom |
| 5985749 |
Method of forming a via hole structure including CVD tungsten silicide barrier layer |
November 16, 1999 |
| The invention relates to integrated circuits and to via hole structures which include a tungsten silicide barrier layer and to methods of forming such via hole structures. In an exemplary embodiment, a metal layer is formed on a sidewall and a bottom surface of the via hole, a WSi.sub.x |
| 5981378 |
Reliable interconnect via structures and methods for making the same |
November 9, 1999 |
| Disclosed is an aluminum filled via hole for use in a semiconductor interconnect structure. The aluminum filled via hole of the semiconductor interconnect structure includes a first patterned metallization layer lying over a first dielectric layer. A second dielectric layer overlying |
| 5976987 |
In-situ corner rounding during oxide etch for improved plug fill |
November 2, 1999 |
| A self-aligned contact etch and method for forming a self-aligned contact etch. In one embodiment, the present invention performs an oxide selective etch to form an opening originating at a top surface of a photoresist layer. The opening extends through an underlying oxide layer, and |
| 5965941 |
Use of dummy underlayers for improvement in removal rate consistency during chemical mechanical |
October 12, 1999 |
| A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a |
| 5965218 |
Process for manufacturing ultra-sharp atomic force microscope (AFM) and scanning tunneling micro |
October 12, 1999 |
| A method for manufacturing probe tips suitable for use in an atomic force microscope (AFM) or scanning tunneling microscope (STM) begins by depositing a layer of a first material over a substrate and then patterning the layer of the first material to define apertures wherever probe t |
| 5963784 |
Methods of determining parameters of a semiconductor device and the width of an insulative space |
October 5, 1999 |
| The present invention provides methods of determining a smallest dimension of a fabricated device on a semiconductor substrate, methods of determining width of a structure comprising a refractory metal silicide, methods of determining parameters of a semiconductor device comprising a |
