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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Bol; Igor
Address:
Sherman Oaks, CA
No. of patents:
9
Patents:












Patent Number Title Of Patent Date Issued
7944035 Double sided semiconduction device with edge contact and package therefor May 17, 2011
A semiconductor die has devices such as MOSgated devices, diodes and the like formed into the top and bottom surfaces of the die. One terminal of each of the devices terminal in the interior center of the die and a common contact is made to the interior center of the die at one edge of
7462908 Dynamic deep depletion field effect transistor December 9, 2008
A vertical conduction trench FET has a plurality of trenches containing conductive polysilicon gates. The mesas between the trenches have a source diffusion region connected to a common source electrode. The trenches are spaced so that the depletion regions induced by the trench gate
7319059 High density FET with self-aligned source atop the trench January 15, 2008
A method for manufacturing a power semiconductor device which includes forming a semiconductor region such as a polysilicon layer or epitaxially grown silicon over a region implanted with source implants and applying heat in a thermal step to cause the source implants to diffuse into the
6858499 Method for fabrication of MOSFET with buried gate February 22, 2005
An insulation is formed on a substrate of a material having a first conductivity type. A gate material is formed on the insulation. A portion of the gate material is removed thereby creating forming mesa type gate structures from remaining positions of the gate material. The mesas are
6699775 Manufacturing process for fast recovery diode March 2, 2004
A termination structure and reduced mask process for its manufacture for either a FRED device or any power semiconductor device comprises at least two concentric diffusion guard rings and two spaced silicon dioxide rings used in the definition of the two guard rings. A first metal ring o
6656843 Single mask trench fred with enlarged Schottky area December 2, 2003
A single mask process is described for making a trench type fast recovery process. The single mask defines slots in a photoresist for locally removing strips of nitride and oxide from atop silicon and for subsequently etching trenches in the silicon. A boron implant is carried out in
6570218 MOSFET with a buried gate May 27, 2003
An insulation is formed on a substrate of a material having a first conductivity type. A gate material is formed on the insulation. A portion of the gate material is removed thereby creating forming mesa type gate structures from remaining positions of the gate material. The mesas are
6541820 Low voltage planar power MOSFET with serpentine gate pattern April 1, 2003
A three mask process is described for a low voltage, low on-resistance power MOSFET. A serpentine gate divides a non-epi silicon die into laterally separated drain and source regions with a very large channel width per unit area.
6294445 Single mask process for manufacture of fast recovery diode September 25, 2001
A single mask process for manufacture of a FRED employs a thick oxide layer over an N type silicon surface and a thin nitride layer over the oxide. A single mask defines FRED device spaced P diffusions. The oxide spanning the P diffusions is laterally etched away, under the nitride layer










 
 
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