| Patent Number |
Title Of Patent |
Date Issued |
| 6205560 |
Debug system allowing programmable selection of alternate debug mechanisms such as debug handler |
March 20, 2001 |
| A circuit for diagnosing and debugging a processor for executing a stream of instructions that includes a set of debug registers for identifying an instruction or data address breakpoint; a processor for generating a debug exception in response to an instruction or data address in the st |
| 5963984 |
Address translation unit employing programmable page size |
October 5, 1999 |
| Systems and methods for virtual addressing are disclosed having an address translation unit with variable page size by employing direct, victim, and programmable block translation look aside buffers. Selective comparisons between contents on a linear address bus and linear address tags a |
| 5937178 |
Register file for registers with multiple addressable sizes using read-modify-write for register |
August 10, 1999 |
| A microprocessor includes an execution unit for processing a stream of instructions wherein one or more of the instructions reference the eight logical x86 general purpose registers as source and destination registers for operands for the instructions. The microprocessor further includes |
| 5898815 |
I/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and rati |
April 27, 1999 |
| A bus interface unit of a processor comprises an I/O recovery counter for preventing peripheral overrun due to successive I/O bus cycles. The I/O recovery counter counts the necessary I/O recovery period between I/O bus cycles necessary to prevent peripheral overrun. The I/O recovery cou |
| 5838897 |
Debugging a processor using data output during idle bus cycles |
November 17, 1998 |
| A processor for outputting processor state information during idle bus cycles to facilitate the diagnosing and debugging of a processor. The processor includes a plurality of external pins for communicating data from the processor; a visibility register for selecting one of a plurality |
| 5784589 |
Distributed free register tracking for register renaming using an availability tracking register |
July 21, 1998 |
| In a pipelined processor having at least one execution pipeline for executing instructions, the execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages to process instructions for the processor, the processor including a register trans |
| 5771365 |
Condensed microaddress generation in a complex instruction set computer |
June 23, 1998 |
| A microarchitecture in a complex instruction computer system is disclosed employing a sparse microROM array and concatenation address circuitry for forming microaddress entry points, avoiding the need for a programmable logic array to translate instruction opcodes and avoiding duplicativ |
| 5664149 |
Coherency for write-back cache in a system designed for write-through cache using an export/inva |
September 2, 1997 |
| A write-back coherency system, including FLUSH/INVAL and LOCK protocols, is used, in an exemplary embodiment, in a microprocessor used in a computer system that selectively provides to the processor FLUSH and INVAL signals to implement a limited write-back protocol. The FLUSH/INVAL proto |
| 5644741 |
Processor with single clock decode architecture employing single microROM |
July 1, 1997 |
| A processor includes storage circuitry for storing an instruction and memory circuitry addressable by a microaddress for outputting a microinstruction in response to the microaddress. The processor further includes sequencing circuitry coupled to provide the microaddress to the memor |
| 5596731 |
Single clock bus transfers during burst and non-burst cycles |
January 21, 1997 |
| A single block bus transfer (SCBT) protocol is implemented, in an exemplary embodiment, in a computer system that includes an .times.86 microprocessor, system logic, and an external memory subsystem including L2 cache and system DRAM, intercoupled by a 586 bus architecture. The micro |
