| Patent Number |
Title Of Patent |
Date Issued |
| 7509512 |
Instruction-initiated method for suspending operation of a pipelined data processor |
March 24, 2009 |
| An instruction-initiated method for suspending operation of a pipelined data processor by selectively disabling a clock signal to pipeline subcircuitry in response to an instruction executed by the pipeline subcircuitry. |
| 7120810 |
Instruction-initiated power management method for a pipelined data processor |
October 10, 2006 |
| An instruction-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to an instruction executed by the pipeline subcircuitry. |
| 7062666 |
Signal-initiated method for suspending operation of a pipelined data processor |
June 13, 2006 |
| A signal-initiated method for suspending operation of a pipelined data processor by selectively disabling a clock signal to pipeline subcircuitry in response to at least one control signal. |
| 7000132 |
Signal-initiated power management method for a pipelined data processor |
February 14, 2006 |
| A signal-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to at least one control signal. |
| 6978390 |
Pipelined data processor with instruction-initiated power management control |
December 20, 2005 |
| A pipelined data processor with instruction-initiated power management control in which a plurality of subcircuits, including pipeline subcircuitry and circuitry for generating and controlling at least one clock signal are responsive to an instruction executed by the pipeline subcirc |
| 6910141 |
Pipelined data processor with signal-initiated power management control |
June 21, 2005 |
| A pipelined data processor with signal-initiated power management control in which a plurality of subcircuits, including pipeline subcircuitry, and circuitry for generating and controlling at least one clock signal are responsive to at least one control signal by disabling a clock signal |
| 6721894 |
METHOD FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL |
April 13, 2004 |
| In accordance with the presently claimed invention, power consumption reduction control is provided to a processor used to execute instructions for data processing. A power management control signal is provided to the processor in accordance with conditions associated with the processor |
| 6694443 |
SYSTEM FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL |
February 17, 2004 |
| Power consumption reduction control circuitry external and coupled to a processor used to execute instructions for data processing. A power management control signal is provided to the processor in accordance with conditions associated with the processor being operated in normal and |
| 6343363 |
Method of invoking a low power mode in a computer system using a halt instruction |
January 29, 2002 |
| A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instr |
| 6138230 |
Processor with multiple execution pipelines using pipe stage state information to control indepe |
October 24, 2000 |
| A microprocessor comprises a plurality of instruction pipelines having a plurality of stages for processing a stream of instructions, circuitry for simultaneously issuing instructions into two or more of the pipelines without regard to whether one of the simultaneously issued instructions |
| 6088807 |
Computer system with low power mode invoked by halt instruction |
July 11, 2000 |
| A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instr |
| 6073231 |
Pipelined processor with microcontrol of register translation hardware |
June 6, 2000 |
| A microprocessor comprises one or more instruction pipelines having a plurality of stages for processing a stream of instructions, with one or more of said instructions referencing a set of logical registers. A plurality of physical registers are allocated to store data associated wi |
| 5907860 |
System and method of retiring store data from a write buffer |
May 25, 1999 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
| 5860111 |
Coherency for write-back cache in a system designed for write-through cache including export-on- |
January 12, 1999 |
| A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DM |
| 5632037 |
Microprocessor having power management circuitry with coprocessor support |
May 20, 1997 |
| A processing unit includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detecting circuitry detects the assertion of a first signal indicative of a request for suspending operation of the processing unit and the assertion of a second signal indicatin |
| 5630149 |
Pipelined processor with register renaming hardware to accommodate multiple size registers |
May 13, 1997 |
| A microprocessor comprises one or more instruction pipelines having a plurality of stages for processing a stream of instructions, wherein one or more of the instructions reference a defined set of logical registers having multiple addressable sizes as sources and destinations of operand |
| 5630143 |
Microprocessor with externally controllable power management |
May 13, 1997 |
| A processing unit includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detection circuitry detects the assertion of a control signal and disabling circuitry is operable to disable the clock signals to one or more of the subcircuits responsive to the |
| 5584009 |
System and method of retiring store data from a write buffer |
December 10, 1996 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
| 5524234 |
Coherency for write-back cache in a system designed for write-through cache including write-back |
June 4, 1996 |
| A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DM |
| 5479616 |
Exception handling for prefetched instruction bytes using valid bits to identify instructions th |
December 26, 1995 |
| An exception handling system is used, in an exemplary embodiment, to provide exception handling for prefetched instruction bytes in a pipelined 486-type microprocessor. The microprocessor includes a prefetch unit (22) that controls the loading of a prefetch queue (24), including appendin |
| 5375209 |
Microprocessor for selectively configuring pinout by activating tri-state device to disable inte |
December 20, 1994 |
| A microprocessor has a plurality of input/output pins and processing coupled to the input/output pins. Circuitry is provided for selectively decoupling the processing circuitry with one or more of the input/output pins such that pins associated with enhanced features may be decoupled to |
| 5159210 |
Line precharging circuits and methods |
October 27, 1992 |
| A bus precharge circuit is provided that precharges a bus line or node as an inverse function of the precharge level already attained on the bus line, such that the precharge level on the bus line is gradually approached. The precharge circuit charges the bus line to a midpoint betwe |
