| Patent Number |
Title Of Patent |
Date Issued |
| 6076155 |
Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between |
June 13, 2000 |
| A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may be to transferred from a CISC |
| 5951702 |
RAM-like test structure superimposed over rows of macrocells with added differential pass transi |
September 14, 1999 |
| A test structure is added to a microprocessor. The test structure is a RAM-like array of scan-clock word lines which selects a row of macrocells to be read or written. Perpendicular to the scan-clock word lines and the rows of macrocells are scan-data bit lines. Each testable macrocell h |
| 5935198 |
Multiplier with selectable booth encoders for performing 3D graphics interpolations with two mul |
August 10, 1999 |
| A multiplier array is modified to perform interpolations. The interpolations use a normalized first operand A between 0 and 1. The interpolation is the function B * A+C * (1-A). Standard multipliers accept two operands as inputs, but interpolations require 3 operands (A, B, C). The A |
| 5884057 |
Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a loa |
March 16, 1999 |
| A processor that can execute both CISC and RISC instructions has an integer pipeline and a floating point pipeline. RISC instructions are sent to the floating point pipeline at the beginning of the integer pipeline, but CISC instructions re-align the floating point pipeline. CISC instruc |
| 5848264 |
Debug and video queue for multi-processor chip |
December 8, 1998 |
| A microprocessor die contains several processor cores and a shared cache. Trigger conditions for one or more of the processor cores are programmed into debug registers. When a trigger is detected, a trace record is generated and loaded into a debug queue on the microprocessor die. Severa |
| 5828578 |
Microprocessor with a large cache shared by redundant CPUs for increasing manufacturing yield |
October 27, 1998 |
| Manufacturing yield is increased and cost lowered when a second, substantially identical CPU core is placed on a microprocessor die when the die contains a large cache. The large cache is shared among the two CPU cores. When one CPU core is defective, the large cache memory may be us |
| 5826074 |
Extenstion of 32-bit architecture for 64-bit addressing with shared super-page register |
October 20, 1998 |
| A processor has 64-bit operand execution pipelines, but a 32-bit branch pipeline. The branch pipeline contains registers to hold the lower 32-bit sub-addresses of 64-bit target and sequential addresses for conditional branches which have been predicted but not yet resolved. A shared regi |
| 5809272 |
Early instruction-length pre-decode of variable-length instructions in a superscalar processor |
September 15, 1998 |
| A superscalar processor can dispatch two instructions per clock cycle. The first instruction is decoded from instruction bytes in a large instruction buffer. A secondary instruction buffer is loaded with a copy of the first few bytes of the second instruction to be dispatched in a cycle. |
| 5805918 |
Dual-instruction-set CPU having shared register for storing data before switching to the alterna |
September 8, 1998 |
| A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may be transferred from a CISC pro |
| 5790826 |
Reduced register-dependency checking for paired-instruction dispatch in a superscalar processor |
August 4, 1998 |
| The dispatch unit of a superscalar processor checks for register dependencies among instructions to be issued together as a group. The first instruction's destination register is compared to the following instructions' sources, but the destinations of following instructions are not c |
| 5790443 |
Mixed-modulo address generation using shadow segment registers |
August 4, 1998 |
| A mixed-modulo address generation unit has several inputs. The unit effectively adds together a subset of these inputs in a reduced modulus while simultaneously adding other inputs in a full modulus to the partial sum of reduced-modulus inputs. The subset of inputs receives reduced-width |
| 5781750 |
Dual-instruction-set architecture CPU with hidden software emulation mode |
July 14, 1998 |
| A dual-instruction-set CPU is able to execute x86 CISC (complex instruction set computer) code or PowerPC RISC (reduced instruction set computer) code. Three modes of operation are provided: CISC mode, RISC mode, both called user modes, and emulation mode. Emulation mode is entered upon |
| 5781457 |
Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectore |
July 14, 1998 |
| A Boolean logic unit (BLU) features a vectored mux. Boolean instructions are executed by applying operands to the select inputs but truth-table signals to the data inputs. Merge and mask operations are performed by reversing the connection and inputting the operands to the data inputs bu |
| 5745913 |
Multi-processor DRAM controller that prioritizes row-miss requests to stale banks |
April 28, 1998 |
| Memory requests from multiple processors are re-ordered to maximize DRAM row hits and minimize row misses. Requests are loaded into a request queue and simultaneously decoded to determine the DRAM bank of the request. The last row address of the decoded DRAM bank is compared to the row a |
| 5732209 |
Self-testing multi-processor die with internal compare points |
March 24, 1998 |
| A microprocessor die contains several CPU cores that are substantially identical. A large second-level cache on the die is shared among the multiple CPU's. When 3 CPU's are on the die, their outputs are compared during a self-testing mode. If outputs from all three CPU's match, then no |
| 5687336 |
Stack push/pop tracking and pairing in a pipelined processor |
November 11, 1997 |
| A pipelined processor executes several stack instructions simultaneously. Additional shadow registers for stack pointers of instructions in the pipeline are not needed. Instead the new stack pointer is generated once at the end of the pipeline and written to the register file. The stack |
| 5685009 |
Shared floating-point registers and register port-pairing in a dual-architecture CPU |
November 4, 1997 |
| A dual-instruction-set central processing unit (CPU) is capable of executing floating point instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Floating point data is transferred from a CISC p |
| 5664159 |
Method for emulating multiple debug breakpoints by page partitioning using a single breakpoint r |
September 2, 1997 |
| A single breakpoint address register on a CPU is shared to emulate a plurality of breakpoint registers. A plurality of breakpoints are stored in an emulation area of main memory. One of these breakpoints is loaded into the single breakpoint register on the CPU. When a translation-loo |
| 5652872 |
Translator having segment bounds encoding for storage in a TLB |
July 29, 1997 |
| A computer system emulates segment bounds checking with a paging system. Pages entirely within a segment are designated as `clear pages`, while the first and last pages containing segment bounds may be partially-valid pages. The computer system has a memory with a segment descriptor tabl |
| 5634118 |
Splitting a floating-point stack-exchange instruction for merging into surrounding instructions |
May 27, 1997 |
| A stack-register swap or exchange instruction is executed by splitting the exchange into two halves, and then each half is absorbed into a surrounding instruction by translating its source or destination operands. If one or both surrounding instructions are absent, then one or both h |
| 5633819 |
Inexact leading-one/leading-zero prediction integrated with a floating-point adder |
May 27, 1997 |
| The sum from a floating point adder is normalized by an initial shift based on a prediction for the position of the leading one or zero in the sum. This leading-one/zero prediction is based not on the operands input to the adder, nor the result from the adder, but on the intermediate gen |
| 5608886 |
Block-based branch prediction using a target finder array storing target sub-addresses |
March 4, 1997 |
| A target finder array in the instruction cache contains a lower portion of the target address and a block encoding indicating if the target address is within the same 2K-byte block that the branch instruction is in, or if the target address is in the next or previous 2K-byte block. The u |
| 5598553 |
Program watchpoint checking using paging with sub-page validity |
January 28, 1997 |
| Segmentation is added to a reduced instruction set computer (RISC) processor which supports paging. The arithmetic-logic-unit (ALU) is extended to allow for a 3-port addition so that the segment base can be added when the virtual address is being generated. Segment bounds checking is |
| 5598546 |
Dual-architecture super-scalar pipeline |
January 28, 1997 |
| A dual-instruction-set processor processes instructions from two or more instruction sets. The processor has several pipelines for processing different types of operations--Memory, ALU, and Branch operations. Instructions are decoded by RISC and CISC instruction decoders which genera |
| 5551001 |
Master-slave cache system for instruction and data cache memories |
August 27, 1996 |
| A master-slave cache system has a large, set-associative master cache, and two smaller direct-mapped slave caches, a slave instruction cache for supplying instructions to an instruction pipeline of a processor, and a slave data cache for supplying data operands to an execution pipeline o |
| 5548545 |
Floating point exception prediction for compound operations and variable precision using an inte |
August 20, 1996 |
| Exponents are first combined together, in a way that varies with the type of floating point operation. A single intermediate exponent result is placed on an intermediate exponent bus. This intermediate exponent is adjusted upwards for any carry-out from the operation on the mantissas, or |
| 5542109 |
Address tracking and branch resolution in a processor with multiple execution pipelines and inst |
July 30, 1996 |
| An address of any desired instruction in a super-scalar processor is generated using address tracking logic. A sequential address register in the last stage of the processor's pipelines holds the address of the last or oldest instruction in the pipelines. This register is updated with a |
| 5542059 |
Dual instruction set processor having a pipeline with a pipestage functional unit that is reloca |
July 30, 1996 |
| A CPU pipeline is able to process instructions from a complex instruction set computer CISC instruction set and from a reduced instruction set computer RISC set. A mode register is provided to indicate whether RISC or CISC instructions are currently being processed. Two instruction decod |
| 5511017 |
Reduced-modulus address generation using sign-extension and correction |
April 23, 1996 |
| A mixed-modulo address generation unit has several inputs, preferably three. The unit can effectively add together a subset of these inputs in a reduced modulus, and simultaneously add this partial sum to a full-width input using a full modulus, the full modulus being greater than the |
| 5481693 |
Shared register architecture for a dual-instruction-set CPU |
January 2, 1996 |
| A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may be transferred from a CISC pro |
| 5481684 |
Emulating operating system calls in an alternate instruction set using a modified code segment d |
January 2, 1996 |
| The CISC architecture is extended to provide for segments that can hold RISC code rather than just CISC code. These new RISC code segments have descriptors that are almost identical to the CISC segment descriptors, and therefore these RISC descriptors may reside in the CISC descriptor ta |
| 5477082 |
Bi-planar multi-chip module |
December 19, 1995 |
| A bi-planar multi-chip package has die mounted on both sides of an insulating flexible carrier. The die are located in two parallel planes, with the flexible carrier located on a third plane between the two die planes. The die are mounted with the active circuit area facing each other |
| 5455909 |
Microprocessor with operation capture facility |
October 3, 1995 |
| The present invention provides a microprocessor with a special Operation Capture Facility (OCF) mechanism which enables "faulting" whenever there is (a) a memory access request to any one of a specified plurality of blocks of memory (b) a request to access any one of a plurality of s |
| 5440710 |
Emulation of segment bounds checking using paging with sub-page validity |
August 8, 1995 |
| Segmentation is added to a reduced instruction set computer (RISC) processor which supports paging. The arithmetic-logic-unit (ALU) is extended to allow for a 3-port addition so that the segment base can be added when the virtual address is being generated. Segment bounds checking is |
| 5381543 |
Processor system with dual clock |
January 10, 1995 |
| The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequen |
| 5325516 |
Processor system with dual clock |
June 28, 1994 |
| The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequen |
| 5313606 |
System for detecting boundary cross-over of instruction memory space using reduced number of add |
May 17, 1994 |
| An improved system for checking for segmentation violations counts the total number of bytes accessed from the control segment following a control transfer operation. If the count indicates that a part of an instruction is fetched from outside the control segment a limit exception oc |
| 5276825 |
Apparatus for quickly determining actual jump addresses by assuming each instruction of a plural |
January 4, 1994 |
| A method and apparatus for performing a fast jump address calculation is disclosed. A field from the instruction is provided to an adder, on the assumption that it is the displacement value, without actually determining whether it is a displacement value. A fixed instruction length is al |
| 5274791 |
Microprocessor with OEM mode for power management with input/output intiated selection of specia |
December 28, 1993 |
| The present invention provides a microprocessor with a special OEM mode of operation that can be used by an OEM system integrator to implement special tasks such as power management. The OEM mode provided by the present invention is designed for use by a system integrator who integra |
