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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Blaauw; David T.
Address:
Austin, TX
No. of patents:
13
Patents:












Patent Number Title Of Patent Date Issued
7149674 Methods for analyzing integrated circuits and apparatus therefor December 12, 2006
A method of improving performance of a dual V.sub.t integrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit
6819538 Method and apparatus for controlling current demand in an integrated circuit November 16, 2004
The present invention relates generally methods and apparatus for controlling current demand in an integrated circuit. One embodiment relates to a method that includes detecting if a supply voltage overshoot or a undershoot is present or anticipated, and if detected, controlling curr
6799153 Cross coupling delay characterization for integrated circuits September 28, 2004
A solution to perform cross coupling delay characterization for integrated circuits and other microprocessor applications. The invention properly models the integrated circuit in various configurations at various times to accommodate the non-linearities associated with driver circuitry a
6480998 Iterative, noise-sensitive method of routing semiconductor nets using a delay noise threshold November 12, 2002
The invention relates to a new method of guidance for routing of nets in an integrated circuit model wherein all nets are first approximately routed, as with Steiner routing, and victim nets with functional delay noise above predetermined thresholds are identified. Each victim net is the
6195628 Waveform manipulation in time warp simulation February 27, 2001
A system and method for manipulating waveforms, including transaction cancellation, in parallel time-warp simulation of circuits, such as those modeled in VHDL. Events waveforms for each output of a processor are organized by the simulation time (ST) of the events which created them and
5956261 In-transit message detection for global virtual time calculation in parrallel time warp simulati September 21, 1999
System and method for calculating global virtual time for use in memory management, termination detection, snapshots, crash recovery, input and output handling, and so forth, and in parallel simulation of digital circuits. Processes executing on parallel processors communicate messages
5790415 Complementary network reduction for load modeling August 4, 1998
A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (
5787008 Simulation corrected sensitivity July 28, 1998
A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (
5751593 Accurate delay prediction based on multi-model analysis May 12, 1998
A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (
5689432 Integrated circuit design and manufacturing method and an apparatus for designing an integrated November 18, 1997
A method for designing an integrated circuit involves a four step process. First, a behavioral circuit model (BCM) is read which contains assignment statements which identify the logical operation of an integrated circuit (IC). The BCM is translated to a data file which described a plura
5666288 Method and apparatus for designing an integrated circuit September 9, 1997
A method and apparatus for designing and manufacturing integrated circuits (ICs) involves providing an initial library of IC cells (106) and a behavioral circuit model (100) in order to create a gate schematic netlist (102). The gate schematic netlist (102) is optimized by changing i
5619418 Logic gate size optimization process for an integrated circuit whereby circuit speed is improved April 8, 1997
An integrated circuit, when designed, must adhere to timing constraints while attempting to minimize circuit area. In order to adhere to timing specifications while arriving at a near-optimal circuit surface area, an iterative process is used which selectively increases logic gates sizes
5617561 Message sequence number control in a virtual time system April 1, 1997
In a virtual time system employing parallel processing nodes, processor nodes communicate with each other by sending messages. Each message between any pair of processing nodes is labeled with a sequence number, which allows the system to determine which messages are "in-transit" at










 
 
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