| Patent Number |
Title Of Patent |
Date Issued |
| 7555002 |
Infiniband general services queue pair virtualization for multiple logical ports on a single phy |
June 30, 2009 |
| An aliased queue pair is provided within a logically partitioned data processing system for each logical partition for the single general services management queue pair that exists within a physical host channel adapter. Packets intended for the logical ports are received at the phys |
| 7500062 |
Fast path memory read request processing in a multi-level memory architecture |
March 3, 2009 |
| A circuit arrangement and method selectively reorder speculatively issued memory read requests being communicated to a lower memory level in a multi-level memory architecture. In particular, a memory read request that has been speculatively issued to a lower memory level prior to com |
| 7428598 |
Infiniband multicast operation in an LPAR environment |
September 23, 2008 |
| A method, computer program product, and data processing system for providing system-area network (SAN) multicasting functionality in a logically partitioned (LPAR) data processing system in which a channel adapter is shared among a plurality of logical partitions is disclosed. A pref |
| 7296108 |
Apparatus and method for efficient transmission of unaligned data |
November 13, 2007 |
| An apparatus and method to transmit unaligned data over an interface bus while providing the appearance of aligned data transfers to the receiving processor. In a preferred embodiment, an alignment mechanism is provided in the bus interface of the receiving processor to align the data |
| 7283473 |
Apparatus, system and method for providing multiple logical channel adapters within a single phy |
October 16, 2007 |
| An apparatus, system and method for providing multiple logical partitions in a system area network are provided Logical partitioning support is provided for host channel adapters which allows multiple operating systems to share the resources of a single physical host channel adapter |
| 7197536 |
Primitive communication mechanism for adjacent nodes in a clustered computer system |
March 27, 2007 |
| A circuit arrangement, node, clustered computer system, and method incorporate a primitive communication mechanism for use in exchanging data between adjacent nodes coupled via a point-to-point network. A plurality of network ports are used to couple a node to other nodes in the clus |
| 7188198 |
Method for implementing dynamic virtual lane buffer reconfiguration |
March 6, 2007 |
| A method, apparatus and computer program product are provided for implementing dynamic Virtual Lane buffer reconfiguration in a channel adapter. A first register is provided for communicating an adapter buffer size and allocation capability for the channel adapter. At least one secon |
| 7149220 |
System, method, and product for managing data transfers in a network |
December 12, 2006 |
| A method, system, and product in a data processing system are disclosed for managing data transmitted from a first end node to a second end node included in the data processing system. A logical connection is established between the first end node and the second end node prior to tra |
| 7113995 |
Method and apparatus for reporting unauthorized attempts to access nodes in a network computing |
September 26, 2006 |
| A method in a node for managing authorized attempts to access the node. A packet is received from a source, wherein the packet includes a first key. A determination is made as to whether the first key matches a second key for the node. The packet is dropped without a response to the sour |
| 7010633 |
Apparatus, system and method for controlling access to facilities based on usage classes |
March 7, 2006 |
| An apparatus, system and method for controlling access to facilities based on usage class of a requestor are provided. With the apparatus, system and method, a two level protection mechanism is provided for protecting host channel adapter (HCA) facilities from unauthorized access. With t |
| 6978300 |
Method and apparatus to perform fabric management |
December 20, 2005 |
| A method and apparatus to perform network fabric management is provided. The method and apparatus provide a mechanism by which modifications to components of the network fabric may be made without tearing down existing connections. The apparatus and method facilitate such fabric manageme |
| 6938138 |
Method and apparatus for managing access to memory |
August 30, 2005 |
| A method and apparatus for accessing a memory. Access rights for a memory operation are verified using a first data structure in response to receiving a request to perform the operation, wherein the request includes a virtual address for the operation. Responsive to access rights being |
| 6920519 |
System and method for supporting access to multiple I/O hub nodes in a host bridge |
July 19, 2005 |
| Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling routing of DMA data to o |
| 6785759 |
System and method for sharing I/O address translation caching across multiple host bridges |
August 31, 2004 |
| A processor system includes an I/O bus to host bridge in which I/O address translation elements are shared across multiple I/O bus bridges. A TCE manager is provided for retaining in cache a TCE entry associated with a discarded channel for association with a new channel responsive to a |
| 6754753 |
Atomic ownership change operation for input/output (I/O) bridge device in clustered computer sys |
June 22, 2004 |
| A clustered computer system, bridge device and method include support for an atomic ownership change operation that ensures orderly and reliable ownership management of an input/output (I/O) bridge device. A lock indicator is associated with a bridge device, and is used to indicate a |
| 6748499 |
Sharing memory tables between host channel adapters |
June 8, 2004 |
| A method, computer program product, and data processing system for sharing memory protection tables and address translation tables among multiple Host Channel Adapters are disclosed. The protection and address translation tables for a shared memory region are written in memory of the |
| 6691217 |
Method and apparatus for associating memory windows with memory regions in a data storage system |
February 10, 2004 |
| A method, program and system for associating memory windows with memory regions in an infiniband data storage system are provided. The invention comprises registering a Memory Region, wherein the Memory Region is a set of virtually contiguous memory addresses defined by a virtual address |
| 6601148 |
Infiniband memory windows management directly in hardware |
July 29, 2003 |
| A method, system and program for controlling access to memory areas within a computer are provided. The invention comprises placing a first Bind Work Queue Element (WQE) at the head of a work queue, wherein the first Bind WQE defines parameters associated with a first Memory Window. A se |
| 6578122 |
Using an access key to protect and point to regions in windows for infiniband |
June 10, 2003 |
| A method, system and program for controlling access to computer memory are provided. The present invention comprises receiving a work request from a user, wherein the work request comprises an index portion and a protection portion. The index portion of the work request is used to locate |
| 6529991 |
Ordering mechanism, ordering method and computer program product for implementing PCI peer to fu |
March 4, 2003 |
| An ordering mechanism, ordering method and computer program product are provided for implementing PCI local bus (PCI) peer to peer functions. When a read command is received, checking for available resource is performed. Responsive to not identifying available resource, a retry read comm |
| 6275876 |
Specifying wrap register for storing memory address to store completion status of instruction to |
August 14, 2001 |
| A computing system includes a processing system, at least a first register, and a control system. The processing system generates a first instruction set and a first address for storing a first completion status for the first instruction set. The first register receives the first address |
| 6185642 |
Bus for high frequency operation with backward compatibility and hot-plug ability |
February 6, 2001 |
| A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first |
| 6128674 |
Method of minimizing host CPU utilization in driving an adapter by residing in system memory a c |
October 3, 2000 |
| The system I/O interface and its data structure are designed to minimize the host CPU utilization in driving an adapter. The interface is also designed to reduce the system interference in processing I/O requests. To eliminate the need of using PIO instructions, the command/status blocks |
| 5781763 |
Independent control of DMA and I/O resources for mixed-endian computing systems |
July 14, 1998 |
| A mixed-endian computer system enhanced to manage I/O DMA without a software DMA performance penalty. A mixed-endian computer system can change endian mode on a task by task basis if necessary. The mixed-endian system, as enhanced, performs one of two well-defined DMA operations based |
