| Patent Number |
Title Of Patent |
Date Issued |
| 7572705 |
Semiconductor device and method of manufacturing a semiconductor device |
August 11, 2009 |
| A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion |
| 7456062 |
Method of forming a semiconductor device |
November 25, 2008 |
| A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subs |
| 7422961 |
Method of forming isolation regions for integrated circuits |
September 9, 2008 |
| A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low |
| 7407882 |
Semiconductor component having a contact structure and method of manufacture |
August 5, 2008 |
| A semiconductor component having a titanium silicide contact structure and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a semiconductor substrate. An opening having sidewalls is formed in the dielectric layer and exposes a portion |
| 7405112 |
Low contact resistance CMOS circuits and methods for their fabrication |
July 29, 2008 |
| A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first transition metal elec |
| 7402207 |
Method and apparatus for controlling the thickness of a selective epitaxial growth layer |
July 22, 2008 |
| Methods and systems for permitting thickness control of the selective epitaxial growth (SEG) layer in a semiconductor manufacturing process, for example raised source/drain applications in CMOS technologies, are presented. These methods and systems provide the capability to measure t |
| 7312125 |
Fully depleted strained semiconductor on insulator transistor and method of making the same |
December 25, 2007 |
| An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and a buried oxide la |
| 7307322 |
Ultra-uniform silicide system in integrated circuit technology |
December 11, 2007 |
| A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed |
| 7217660 |
Method for manufacturing a semiconductor component that inhibits formation of wormholes |
May 15, 2007 |
| A method for manufacturing a semiconductor component that inhibits formation of wormholes in a semiconductor substrate. A contact opening is formed in a dielectric layer disposed on a semiconductor substrate. The contact opening exposes a portion of the semiconductor substrate. A sac |
| 7169706 |
Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper depositio |
January 30, 2007 |
| An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor |
| 7151020 |
Conversion of transition metal to silicide through back end processing in integrated circuit tec |
December 19, 2006 |
| A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is for |
| 7132352 |
Method of eliminating source/drain junction spiking, and device produced thereby |
November 7, 2006 |
| A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A metallic layer is formed on the semiconductor substrate, and the metallic layer is reacted with |
| 7060571 |
Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate diele |
June 13, 2006 |
| Microminiaturized semiconductor devices are fabricated with a replacement metal gate and a high-k tantalum oxide or tantalum oxynitride gate dielectric with significantly reduced carbon. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing |
| 7049666 |
Low power pre-silicide process in integrated circuit technology |
May 23, 2006 |
| A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is form |
| 7033888 |
Engineered metal gate electrode |
April 25, 2006 |
| A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such |
| 7005376 |
Ultra-uniform silicides in integrated circuit technology |
February 28, 2006 |
| A method of forming and a structure of an integrated circuit are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uni |
| 7005357 |
Low stress sidewall spacer in integrated circuit technology |
February 28, 2006 |
| A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed aro |
| 7001837 |
Semiconductor with tensile strained substrate and method of making the same |
February 21, 2006 |
| An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer |
| 6992004 |
Implanted barrier layer to improve line reliability and method of forming same |
January 31, 2006 |
| A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided |
| 6979642 |
Method of self-annealing conductive lines that separates grain size effects from alloy mobility |
December 27, 2005 |
| A method of forming a conductive structure such as a copper conductive structure, line, or via is optimized for large grain growth and distribution of alloy elements. The alloy elements can reduce electromigration problems associated with the conductive structure. The conductive stru |
| 6969678 |
Multi-silicide in integrated circuit technology |
November 29, 2005 |
| A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconduc |
| 6951220 |
Method of decontaminating equipment |
October 4, 2005 |
| A method of performing decontamination of a chamber for use in an IC fabrication system includes providing wet oxygen or a mixture comprising hydrochloric gas and oxygen in the chamber and raising the temperature in the chamber from a first lower temperature to a second higher temperatur |
| 6943569 |
Method, system and apparatus to detect defects in semiconductor devices |
September 13, 2005 |
| A method and system to locate and detect voids in films that are involved in critical dimension (CD) structures and non-critical dimension structures in semiconductor devices are presented. One or more test structures (resolution devices) are formed on a semiconductor wafer. A scanni |
| 6893910 |
One step deposition method for high-k dielectric and metal gate electrode |
May 17, 2005 |
| A method for forming a semiconductor structure removes the temporary gate formed on the dielectric layer to expose a recess in which oxygen-rich CVD oxide is deposited. A tantalum layer is then deposited by low-power physical vapor deposition on the CVD oxide. Annealing is then performed |
| 6878592 |
Selective epitaxy to improve silicidation |
April 12, 2005 |
| A transistor architecture utilizes a raised source and drain region to reduce the adverse affects of germanium on silicide regions. Epitaxial growth can form a silicide region above the source and drain. The protocol can utilize any number of silicidation processes. The protocol allows |
| 6867428 |
Strained silicon NMOS having silicon source/drain extensions and method for its fabrication |
March 15, 2005 |
| An n-type strained silicon MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon regions are provided in the silicon geranium layer at opposing sides of the strained silicon channel region, and shallow source and drain extensions are impla |
| 6861350 |
Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode |
March 1, 2005 |
| Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 .ANG. to 75 .ANG., and then introduc |
| 6861349 |
Method of forming an adhesion layer with an element reactive with a barrier layer |
March 1, 2005 |
| A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a |
| 6858503 |
Depletion to avoid cross contamination |
February 22, 2005 |
| A fabrication system utilizes a protocol for removing germanium from a top surface of a wafer. An exposure to a gas, such as a gas containing the hydrochloric acid can remove germanium from the top surface. The protocol can allow shared equipment to be used in both Flash product fabricat |
| 6835656 |
Method of forming ultra-shallow junctions in a semiconductor wafer with a deposited silicon laye |
December 28, 2004 |
| A method for forming ultra-shallow junctions in a semiconductor wafer with reduced silicon consumption during salicidation supplies additional silicon during the salicidation process. After the gate and source/drain junctions are formed in a semiconductor device, high-resistivity metal |
| 6835655 |
Method of implanting copper barrier material to improve electrical performance |
December 28, 2004 |
| A method of implanting copper barrier material to improve electrical performance in an integrated circuit fabrication process can include providing a copper layer over an integrated circuit substrate, providing a barrier material at a bottom and sides of a via positioned over the copper |
| 6815340 |
Method of forming an electroless nucleation layer on a via bottom |
November 9, 2004 |
| A method of fabricating an integrated circuit can include performing a reactive ion etch (RIE) to form a via aperture in a dielectric layer where the via aperture exposes a portion of a conductive layer located under the dielectric layer, removing polymer residue from the RIE, and formin |
| 6811448 |
Pre-cleaning for silicidation in an SMOS process |
November 2, 2004 |
| A fabrication system utilizes a protocol for removing native oxide from a top surface of a wafer. An exposure to a plasma, such as a plasma containing hydrogen and argon can remove the native oxide from the top surface without causing excessive germanium contamination. The protocol c |
| 6809032 |
Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation usi |
October 26, 2004 |
| In another aspect of the present invention, a system for detecting an endpoint in a polishing process is provided. The system comprises a polishing tool, a controllable light source, a sensor, and a controller. The polishing tool is capable of polishing a surface of a semiconductor d |
| 6797614 |
Nickel alloy for SMOS process silicidation |
September 28, 2004 |
| A process of siliciding uses alloys to reduce the adverse affects of germanium on silicide regions. The alloy can include nickel and at least one of vanadium, tantalum, and tungsten. The process can utilize one or two annealing steps. The process allows better silicidation in SMOS de |
| 6787864 |
Mosfets incorporating nickel germanosilicided gate and methods for their formation |
September 7, 2004 |
| A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in |
| 6784506 |
Silicide process using high K-dielectrics |
August 31, 2004 |
| A method for preventing the thermal decomposition of a high-K dielectric layer of a gate electrode during the formation of a metal silicide on the gate electrode by using nickel as the metal component of the silicide. |
| 6764912 |
Passivation of nitride spacer |
July 20, 2004 |
| The formation of metal silicides in silicon nitride spacers on a gate electrode causes bridging between a gate electrode and the source and drain regions of a semiconductor device. The bridging is prevented by forming a thin layer of silicon oxide on the silicon nitride spacers prior |
| 6730576 |
Method of forming a thick strained silicon layer and semiconductor structures incorporating a th |
May 4, 2004 |
| A strained silicon layer is grown on a layer of silicon germanium and a layer of silicon germanium is grown on the strained silicon in a single continuous in situ deposition process with the strained silicon. Shallow trench isolations are formed in the lower layer of silicon germanium pr |
| 6727560 |
Engineered metal gate electrode |
April 27, 2004 |
| A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such tha |
| 6724087 |
Laminated conductive lines and methods of forming the same |
April 20, 2004 |
| A method of fabricating an integrated circuit can include forming a laminated conductive line. The laminated conductive line can be formed in a dielectric trench. The laminated conductive line can include alternating barrier layers and copper layers. An integrated circuit includes at lea |
| 6703308 |
Method of inserting alloy elements to reduce copper diffusion and bulk diffusion |
March 9, 2004 |
| A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a |
| 6703307 |
Method of implantation after copper seed deposition |
March 9, 2004 |
| A method of fabricating an integrated circuit can include forming a barrier layer along lateral side walls and a bottom of a via aperture, forming a seed layer proximate and conformal to the barrier layer, and forming an implanted layer proximate and conformal to the barrier layer and th |
| 6660621 |
Method of forming ultra-shallow junctions in a semiconductor wafer with silicon layer deposited |
December 9, 2003 |
| A method of forming ultra-shallow junctions in a semiconductor wafer forms the gate and source/drain junctions having upper surfaces at first metal suicide regions on the gate and source/drain junctions. These first metal silicide regions have a higher resistivity. Amorphous silicon is d |
| 6656836 |
Method of performing a two stage anneal in the formation of an alloy interconnect |
December 2, 2003 |
| A method of performing a two stage anneal in the formation of an alloy interconnect can include forming a via aperture in a dielectric layer where the via aperture provides an area for formation of a via, providing a seed layer along lateral side walls of the via aperture, rapid thermal |
| 6656834 |
Method of selectively alloying interconnect regions by deposition process |
December 2, 2003 |
| A metal interconnect structure and method for making the same provides an alloying elements layer that lines a via in a dielectric layer. The alloying element layer is therefore inserted at a critical electromigration failure site, i.e., at the fast diffusion site below the via in th |
| 6633085 |
Method of selectively alloying interconnect regions by ion implantation |
October 14, 2003 |
| A metal interconnect structure and method of making the same implants ions of an alloy elements into a copper line through a via. Then ion implantation of the alloy elements in the copper line through the via provides improved electromigration properties at the copper line at a criti |
| 6629879 |
Method of controlling barrier metal polishing processes based upon X-ray fluorescence measuremen |
October 7, 2003 |
| The present invention is directed to a method of controlling polishing processes based upon x-ray fluorescence measurements. In one illustrative embodiment, the method comprises providing a wafer comprised of a layer of insulating material having a barrier metal layer formed thereabove a |
| 6617176 |
METHOD OF DETERMINING BARRIER LAYER EFFECTIVENESS FOR PREVENTING METALLIZATION DIFFUSION BY FORM |
September 9, 2003 |
| A method (M) of determining the effectiveness of a deposited thin conformal barrier layer (30) by forming a test specimen and measuring the copper (Cu) penetration from a metallization layer (40) through the barrier layer (30) (e.g., refractory metals, their nitrides, their carbides, or |
| 6614064 |
Transistor having a gate stick comprised of a metal, and a method of making same |
September 2, 2003 |
| The present invention is generally directed to a transistor having a gate stack comprised of a metal, and a method of making same. In one illustrative embodiment, the transistor is comprised of a gate stack comprised of a gate insulation layer positioned above a semiconducting substr |
