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Inventor:
Benson; Peter A.
Address:
Boise, ID
No. of patents:
21
Patents:












Patent Number Title Of Patent Date Issued
8192555 Non-chemical, non-optical edge bead removal process June 5, 2012
A method for removing the edge bead from a substrate by applying an impinging stream of a medium that is not a solvent for the material to be removed. The medium is applied to the periphery of the substrate with sufficient force to remove the material. Also an apparatus to perform the
7994547 Semiconductor devices and assemblies including back side redistribution layers in association wi August 9, 2011
Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the active surface devices of a semiconductor substrate using through wafer interconnects (TWIs). The TWIs may be formed prior to f
7759800 Microelectronics devices, having vias, and packaged microelectronic devices having vias July 20, 2010
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the
7709776 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic i May 4, 2010
Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external
7615119 Apparatus for spin coating semiconductor substrates November 10, 2009
An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming and using such a structure. In one embodiment, a wafer edge ring is formed using a stereolithography (STL) process. In another
7583358 Systems and methods for retrieving residual liquid during immersion lens photolithography September 1, 2009
Systems and methods for retrieving residual liquid during immersion lens photolithography are disclosed. A method in accordance with one embodiment includes directing radiation along a radiation path, through a lens and through a liquid volume in contact with the lens, to a microfeat
7579684 Methods for packing microfeature devices and microfeature devices formed by such methods August 25, 2009
Methods for packaging microfeature devices on and/or in microfeature workpieces at the wafer level and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method comprises providing a workpiece including a substrate having a plurality of
7504615 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic i March 17, 2009
Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external
7489020 Semiconductor wafer assemblies February 10, 2009
An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming and using such a structure. In one embodiment, a wafer edge ring is formed using a stereolithography (STL) process. In another
7435620 Low temperature methods of forming back side redistribution layers in association with through w October 14, 2008
Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the active surface devices of a semiconductor substrate using through wafer interconnects (TWIs). The TWIs may be formed prior to f
7419852 Low temperature methods of forming back side redistribution layers in association with through w September 2, 2008
Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the active surface devices of a semiconductor substrate using through wafer interconnects (TWIs). The TWIs may be formed prior to f
7419841 Microelectronic imagers and methods of packaging microelectronic imagers September 2, 2008
Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electricall
7413979 Methods for forming vias in microelectronic devices, and methods for packaging microelectronic d August 19, 2008
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the
7265330 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic i September 4, 2007
Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external
7253957 Integrated optics units and methods of manufacturing integrated optics units for use with microe August 7, 2007
Microelectronic imagers, optical devices for microelectronic imagers, methods for manufacturing integrated optical devices for use with microelectronic imagers, and methods for packaging microelectronic imagers. The optical devices are manufactured in optical device assemblies that p
7244665 Wafer edge ring structures and methods of formation July 17, 2007
An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming and using such a structure. In one embodiment, a wafer edge ring is formed using a stereolithography (STL) process. In another
7239933 Substrate supports for use with programmable material consolidation apparatus and systems July 3, 2007
A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one fabrication site. The at least one fabrication site may be configured to receive one or more fabrication substrates, such as semic
7225044 Methods for supporting substrates during fabrication of one or more objects thereon by programma May 29, 2007
A programmed material consolidation apparatus includes a support with a surface that receives at least one substrate and prevents unconsolidated material from contacting undesired regions, such as the bottom surface, of the at least one substrate. When a programmed material consolidation
7199439 Microelectronic imagers and methods of packaging microelectronic imagers April 3, 2007
Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electricall
7189954 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic i March 13, 2007
Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external
7091124 Methods for forming vias in microelectronic devices, and methods for packaging microelectronic d August 15, 2006
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the










 
 
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