| Patent Number |
Title Of Patent |
Date Issued |
| RE38610 |
Host CPU independent video processing unit |
October 5, 2004 |
| The present invention relates to a video display processor comprised apparatus for receiving digital input signal components of a signal to be displayed, apparatus for converting the components to a desired format, apparatus for scaling and blending the signals in the desired format, |
| 5828475 |
Bypass switching and messaging mechanism for providing intermix data transfer for a fiber optic |
October 27, 1998 |
| A system and method for inserting intermix frames into a continuous stream of class 1 frames. A bypass bus, in conjunction with a buffer, are provided within a fiber optic switch element, to route intermix data frame through the switch that is concurrently transmitting class 1 data. A |
| 5793445 |
Host CPU independent video processing unit |
August 11, 1998 |
| The present invention relates to a video display processor comprised apparatus for receiving digital input signal components of a signal to be displayed, apparatus for converting the components to a desired format, apparatus for scaling and blending the signals in the desired format, |
| 5764238 |
Method and apparatus for scaling and blending an image to be displayed |
June 9, 1998 |
| The present invention relates to an image scaler comprised of apparatus for receiving coefficients a and b and image display values of adjacent pixels P and Q respective of an image, apparatus for repeatedly operating on the coefficients and values for successive pixels according to the |
| 5603064 |
Channel module for a fiber optic switch with bit sliced memory architecture for data frame stora |
February 11, 1997 |
| A channel module has an interchangeable port intelligence system at a front end which is connected to a memory interface system at a back end. Each port intelligence system provides one or more ports for connection to fiber optic channels and, the various port intelligence systems are |
| 5490007 |
Bypass switching and messaging mechanism for providing intermix data transfer for a fiber optic |
February 6, 1996 |
| A system and method for inserting intermix frames into a continuous stream of class 1 frames. A bypass bus, in conjunction with a first-in-first-out (FIFO) buffer, are provided within a fiber optic switch element, to route intermix data frame through the switch that is concurrently trans |
