| Patent Number |
Title Of Patent |
Date Issued |
| 7623000 |
Hybrid linear and polar modulation apparatus |
November 24, 2009 |
| The invention is directed at a hybrid modulation apparatus which combines a polar modulation circuit and a linear modulation circuit. The hybrid apparatus allows a communications device to function as a polar or a linear modulation circuit with less components as the output of the li |
| 7593701 |
Low noise CMOS transmitter circuit with high range of gain |
September 22, 2009 |
| A CMOS automatic gain control (AGC) circuit that receives an analog control voltage and generates a temperature compensated gain voltage to linearly control the gain of a variable gain circuit operating in the sub-threshold region. A PTAT circuit having a resistor network coupled to |
| 7554380 |
System for reducing second order intermodulation products from differential circuits |
June 30, 2009 |
| A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product g |
| 7509101 |
Method and apparatus for reducing leakage in a direct conversion transmitter |
March 24, 2009 |
| Methods and apparatus for reducing the amount of leakage in a transmitter are disclosed. In one embodiment, a wireless transmitter is comprises: a divider providing a local oscillation (LO) signal, a plurality of mixers that receive the LO signal and receive a signal to be modulated, a s |
| 7376400 |
System and method for digital radio receiver |
May 20, 2008 |
| A communications system comprising a processor, a variable oscillator, a radio frequency (RF) quadrature demodulator, a variable capacitor, a continuous-time, sigma-delta analog-to-digital converter (ADC), and a frequency divider, all integrated on a single semiconductor chip. The ADC |
| 7345550 |
Type II phase locked loop using dual path and dual varactors to reduce loop filter components |
March 18, 2008 |
| A phase locked loop (PLL) with reduced loop filter components having dual charge pumps and corresponding dual signal paths that reduce on-chip component size within the filters. The dual paths are combined advantageously via dual varactors within a voltage controlled oscillator to fu |
| 7286019 |
Method and system for amplifying a signal |
October 23, 2007 |
| According to one embodiment of the invention, an amplifier includes a gate bias circuit operable to generate a gate bias voltage and a common gate amplifier that includes a transistor having a gate biased by an output of the gate bias circuit and also having a source connected to an indu |
| 7151473 |
Digital detection of blockers for wireless receiver |
December 19, 2006 |
| A receiver 100 is provided. The receiver 100 comprises an in-phase analog-to-digital converter 112 operable to detect a saturation condition of the in-phase analog-to-digital converter 112 and to adjust the amplitude of a in-phase signal processed by the in-phase analog-to-digital co |
| 7095819 |
Direct modulation architecture for amplitude and phase modulated signals in multi-mode signal tr |
August 22, 2006 |
| Multiple-mode direct phase/amplitude modulation circuitry (20) for use in a transceiver (17) of a device such as a wireless handset (10) is disclosed. The modulation circuitry (20) includes a modulation loop (36) for modulating a phase signal into a Gaussian-Minimum-Shift-Keyed (GMSK) |
| 7061989 |
Fully digital transmitter including a digital band-pass sigma-delta modulator |
June 13, 2006 |
| A digital transmitter (20) that may be advantageously used in a high-frequency transceiver, such as a wireless telephone handset, is disclosed. The transmitter (20) includes digital upconverter functions (36I, 36Q) that operate in combination with a digital band-pass sigma-delta modu |
| 6985028 |
Programmable linear-in-dB or linear bias current source and methods to implement current reducti |
January 10, 2006 |
| Programmable linear-in-dB or linear bias current source with respect to an input voltage is provided. The linear-in-dB or linear bias current may be clipped at a minimum current level, a maximum current level, or a combination thereof. Preferably, the minimum and maximum current levels |
