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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Becker; Scott T.
Address:
Scotts Valley, CA
No. of patents:
44
Patents:












Patent Number Title Of Patent Date Issued
8587034 Integrated circuit including cross-coupled transistors having gate electrodes formed within gate November 19, 2013
A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from respective originating rectangular-shaped layout features having its centerline aligned parallel to a first direction. The conductive features form gate electrodes o
8581304 Integrated circuit including cross-coupled transistors having gate electrodes formed within gate November 12, 2013
A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from respective originating rectangular-shaped layout features having its centerline aligned parallel to a first direction. The conductive features form gate electrodes o
8581303 Integrated circuit including cross-coupled trasistors having gate electrodes formed within gate November 12, 2013
A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective
8575706 Integrated circuit including cross-coupled transistors having gate electrodes formed within gate November 5, 2013
First and second p-type diffusion regions, and first and second n-type diffusion regions are formed in a semiconductor device. Each diffusion region is electrically connected to a common node. Gate electrodes are formed from conductive features that are each defined within any one gate
8569841 Integrated circuit including cross-coupled transistors having gate electrodes formed within gate October 29, 2013
A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Conductive features are each defined within any one gate level channel that is uniquely associated with and
8564071 Integrated circuit including cross-coupled transistors having gate electrodes formed within gate October 22, 2013
A semiconductor device includes a substrate having a plurality of diffusion regions defined therein to form first and second p-type diffusion regions, and first and second n-type diffusion regions, with each of these diffusion regions electrically connected to a common node. The firs
8286107 Methods and systems for process compensation technique acceleration October 9, 2012
Selected cells in a semiconductor chip layout are replaced with corresponding PCT pre-processed cells. Each PCT pre-processed cell represents a particular selected cell having been previously subjected to a cell-level-PCT-processing operation so as to include PCT-based cell layout ad
8283701 Semiconductor device with dynamic array sections defined and placed according to manufacturing a October 9, 2012
An integrated circuit device includes a plurality of dynamic array sections, each of which includes three or more linear conductive segments formed within its gate electrode level in a parallel manner to extend lengthwise in a first direction. An adjoining pair of dynamic array secti
8274099 Integrated circuit including cross-coupled transistors having gate electrodes formed within gate September 25, 2012
A semiconductor device includes conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS tran
8264049 Integrated circuit including cross-coupled transistors with two transistors of different type ha September 11, 2012
A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective
8264044 Integrated circuit including cross-coupled transistors having two complementary pairs of co-alig September 11, 2012
Each of first and second PMOS transistors, and first and second NMOS transistors has a respective diffusion terminal with a direct electrical connection to a common node, and has a respective gate electrode formed from an originating rectangular-shaped layout feature. Centerlines of the
8258581 Integrated circuit including cross-coupled transistors with two transistors of different type fo September 4, 2012
A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective
8247846 Oversized contacts and vias in semiconductor chip defined by linearly constrained topology August 21, 2012
A rectangular-shaped interlevel connection structure is defined to electrically connect a first structure in a first chip level with a second structure in a second chip level. The rectangular-shaped interlevel connection structure is defined by an as-drawn cross-section having at lea
8245180 Methods for defining and using co-optimized nanopatterns for integrated circuit design and appar August 14, 2012
A set of layout nanopatterns is defined. Each layout nanopattern is defined by relative placements of a particular type of layout feature within a lithographic window of influence. A design space is defined as a set of layout parameters and corresponding value ranges that affect manu
8225261 Methods for defining contact grid in dynamic array architecture July 17, 2012
First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout fe
8225239 Methods for defining and utilizing sub-resolution features in linear topology July 17, 2012
Regular layout shapes are placed in accordance with a virtual grate. A determination is made as to whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape, is large enough to support
8214778 Methods for cell phasing and placement in dynamic array architecture and implementation of the s July 3, 2012
A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relation
8089098 Integrated circuit device and associated layout including linear gate electrodes of different tr January 3, 2012
A restricted layout region in a layout of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline
8058691 Semiconductor device including cross-coupled transistors formed from linear-shaped gate level fe November 15, 2011
A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective
8058671 Semiconductor device having at least three linear-shaped electrode level conductive features of November 15, 2011
A semiconductor device includes a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of co
8035133 Semiconductor device having two pairs of transistors of different types formed from shared linea October 11, 2011
A semiconductor device includes a substrate portion having a plurality of diffusion regions defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. A gate electrode level region is formed above the substrate portion to include a number of
8030689 Integrated circuit device and associated layout including separated diffusion regions of differe October 4, 2011
A semiconductor device includes a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of co
8022441 Semiconductor device and associated layouts having transistors formed from six linear conductive September 20, 2011
A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a
7994545 Methods, structures, and designs for self-aligning local interconnects used in integrated circui August 9, 2011
Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates are designed to be active gates and some of the plurality of gates are designed to be formed over isol
7989848 Semiconductor device having at least four side-by-side electrodes of equal length and equal pitc August 2, 2011
A substrate portion of a semiconductor device is formed to include a plurality of diffusion regions that are defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. A gate electrode level region is formed above the substrate portion to
7989847 Semiconductor device having linear-shaped gate electrodes of different transistor types with uni August 2, 2011
A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least on
7956421 Cross-coupled transistor layouts in restricted gate level layout architecture June 7, 2011
A first P channel transistor and a first N channel transistor are defined by first and second gate electrodes, respectively. The second gate electrode is electrically connected to the first gate electrode. A second P channel transistor and a second N channel transistor are defined by
7952119 Semiconductor device and associated layout having three or more linear-shaped gate electrode lev May 31, 2011
A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least on
7948013 Semiconductor device and associated layouts having linear shaped gate electrodes defined along a May 24, 2011
A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes to be formed within a portion of a substrate, including a p-type diffusion region layout shape and an n-type diffusion region layout shape
7948012 Semiconductor device having 1965 nm gate electrode level region including at least four active l May 24, 2011
A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least on
7943967 Semiconductor device and associated layouts including diffusion contact placement restriction ba May 17, 2011
A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The plurality of diffusion regions are separated from each other by one or more non-active regions of the substrate portion. The plurality of diffusion regions are defined in a
7943966 Integrated circuit and associated layout with gate electrode level portion including at least tw May 17, 2011
A restricted layout region includes a diffusion level layout including a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type
7939898 Diffusion variability control and transistor device sizing using threshold voltage implant May 10, 2011
A transistor is defined to include a substrate portion and a diffusion region defined in the substrate portion so as to provide an operable transistor threshold voltage. An implant region is defined within a portion of the diffusion region so as to transform the operable transistor t
7939443 Methods for multi-wire routing and apparatus implementing same May 10, 2011
A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set o
7932545 Semiconductor device and associated layouts including gate electrode level region having arrange April 26, 2011
A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a
7932544 Semiconductor device and associated layouts including linear conductive segments having non-gate April 26, 2011
A restricted layout region in a layout of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline
7923757 Semiconductor device and associated layouts having linear shaped gate electrodes defined along a April 12, 2011
A restricted layout region includes a diffusion level layout including p-type and n-type diffusion region layout shapes separated by a central inactive region. The diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the di
7917879 Semiconductor device with dynamic array section March 29, 2011
A semiconductor chip is provided to include one or more distinct but functionally interfaced dynamic array sections. Each dynamic array section follows a dynamic array architecture that requires conductive features to be linearly defined along a virtual grate in each of a plurality o
7910959 Semiconductor device and associated layouts having transistors formed from six linear conductive March 22, 2011
A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel di
7910958 Semiconductor device and associated layouts having transistors formed from linear conductive seg March 22, 2011
A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a
7908578 Methods for designing semiconductor device with dynamic array section March 15, 2011
A method is provided for designing a semiconductor chip having one or more functionally interfaced dynamic array sections. A virtual grate is laid out for conductive features used to define a gate electrode level of a dynamic array section. The virtual grate is defined by a framework of
7906801 Semiconductor device and associated layouts having transistors formed from six linear conductive March 15, 2011
A restricted layout region is defined to include a diffusion level layout that includes a plurality of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The plurality of diffusion region layout shapes are defined in a non-symmetrical m
7888705 Methods for defining dynamic array section with manufacturing assurance halo and apparatus imple February 15, 2011
A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method also includes defining a manufacturing assurance halo outside the boundary of the dynamic
7763534 Methods, structures and designs for self-aligning local interconnects used in integrated circuit July 27, 2010
Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates are designed to be active gates and some of the plurality of gates are designed to be formed over isol










 
 
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