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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Beaman; Kevin L.
Address:
Boise, ID
No. of patents:
32
Patents:












Patent Number Title Of Patent Date Issued
8030170 Methods of forming isolation structures, and methods of forming nonvolatile memory October 4, 2011
Some embodiments include methods of forming isolation structures. A trench may be formed to extend into a semiconductor material. Polysilazane may be formed within the trench, and then exposed to steam. A maximum temperature of the polysilazane during the steam exposure may be less t
8017470 Method of forming a structure over a semiconductor substrate September 13, 2011
The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the sili
7919829 Liner for shallow trench isolation April 5, 2011
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls
7906393 Methods for forming small-scale capacitor structures March 15, 2011
The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second elec
7803678 Method of forming a structure over a semiconductor substrate September 28, 2010
The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the sili
7771537 Methods and systems for controlling temperature during microfeature workpiece processing, E.G. C August 10, 2010
The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method th
7651910 Methods of forming programmable memory devices January 26, 2010
The invention includes a method of forming a programmable memory device. A tunnel oxide is formed to be supported by a semiconductor substrate. A stack is formed over the tunnel oxide. The stack comprises a floating gate, dielectric mass and control gate. The stack has a top, and has
7647886 Systems for depositing material onto workpieces in reaction chambers and methods for removing by January 19, 2010
Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers are disclosed herein. In one embodiment, the system includes a gas phase reaction chamber, a first exhaust line coupled to the reaction chamber, first and s
7514366 Methods for forming shallow trench isolation April 7, 2009
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls
7422635 Methods and apparatus for processing microfeature workpieces, e.g., for depositing materials on September 9, 2008
The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One exemplary implementation provides a method of depositing a reaction product on each of a batch of workpieces positioned in a process
7399714 Method of forming a structure over a semiconductor substrate July 15, 2008
The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the sili
7371647 Methods of forming transistors May 13, 2008
The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the s
7344755 Methods and apparatus for processing microfeature workpieces; methods for conditioning ALD react March 18, 2008
The present disclosure provides methods and apparatus that may be used to process microfeature workpieces, e.g., semiconductor wafers. Some aspects have particular utility in depositing TiN in a batch process. One implementation involves pretreating a surface of a process chamber by
7279398 Microfeature workpiece processing apparatus and methods for controlling deposition of materials October 9, 2007
The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure with
7271464 Liner for shallow trench isolation September 18, 2007
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls
7258892 Methods and systems for controlling temperature during microfeature workpiece processing, e.g., August 21, 2007
The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method th
7235138 Microfeature workpiece processing apparatus and methods for batch deposition of materials on mic June 26, 2007
The present disclosure describes apparatus and methods for processing microfeature workpieces, e.g., by depositing material on a microelectronic semiconductor using atomic layer deposition. Some of these apparatus include microfeature workpiece holders that include gas distributors.
7153736 Methods of forming capacitors and methods of forming capacitor dielectric layers December 26, 2006
A method of forming a capacitor includes forming first capacitor electrode material over a semiconductor substrate. A silicon nitride comprising layer is formed over the first capacitor electrode material. The semiconductor substrate with silicon nitride comprising layer is provided
7056806 Microfeature workpiece processing apparatus and methods for controlling deposition of materials June 6, 2006
The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure with
6815372 Sputtered insulating layer for wordline stacks November 9, 2004
Insulating material is deposited onto a gate dielectric surface separating two wordline stacks, the method comprising the steps of: A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface
6746937 PD-SOI substrate with suppressed floating body effect and method for its fabrication June 8, 2004
A partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and suppressed floating body effect is disclosed, as well as a simple method for its fabrication. A thin Si/Ge epitaxial layer is grown between two adjacent epitaxial silicon layers of a SOI substrate,
6734062 Methods of forming DRAM cells May 11, 2004
The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate including a monocrystalline material is bonded to the first substrate. After the
6723599 Methods of forming capacitors and methods of forming capacitor dielectric layers April 20, 2004
A method of forming a capacitor includes forming first capacitor electrode material over a semiconductor substrate. A silicon nitride comprising layer is formed over the first capacitor electrode material. The semiconductor substrate with silicon nitride comprising layer is provided
6707090 DRAM cell constructions March 16, 2004
The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate containing a monocrystalline material is bonded to the first substrate. After th
6690046 Semiconductor assemblies, methods of forming structures over semiconductor substrates, and metho February 10, 2004
The invention encompasses semiconductor assemblies that include a semiconductor substrate having a first region and a second region defined therein. A first oxide region is on the substrate and covers the first region of the substrate. The first oxide region has nitrogen provided the
6686298 Methods of forming structures over semiconductor substrates, and methods of forming transistors February 3, 2004
The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon
6639243 DRAM cell constructions October 28, 2003
The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate having a monocrystalline material is bonded to the first substrate. After the
6617262 Sputtered insulating layer for wordline stacks September 9, 2003
Insulating material is deposited onto a gate dielectric surface separating two wordline stacks, the method comprising the steps of: A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface
6589843 Methods of forming FLASH field effect transistor gates and non-FLASH field effect transistor gat July 8, 2003
Methods of forming FLASH field effect transistor gates and a non-FLASH field effect transistor gates are described. In one implementation, a substrate comprising first and second semiconductive material portions is provided. A FLASH transistor gate is partially formed to include at least
6455441 Sputtered insulating layer for wordline stacks September 24, 2002
Insulating material is deposited onto a gate dielectric surface separating two wordline stacks, the method comprising the steps of: A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface
6437375 PD-SOI substrate with suppressed floating body effect and method for its fabrication August 20, 2002
A partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and suppressed floating body effect is disclosed, as well as a simple method for its fabrication. A thin Si/Ge epitaxial layer is grown between two adjacent epitaxial silicon layers of a SOI substrate,
6429070 DRAM cell constructions, and methods of forming DRAM cells August 6, 2002
The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate including a monocrystalline material is bonded to the first substrate. After the










 
 
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