| Patent Number |
Title Of Patent |
Date Issued |
| 7343515 |
System and method for performing error recovery in a data processing system having multiple proc |
March 11, 2008 |
| A system and method is disclosed for performing error recovery in a data processing system that supports multiple processing partitions. One or more processors and I/O modules, as well as a portion of the address space of a main memory, is allocated to each partition. In this type of |
| 7277825 |
Apparatus and method for analyzing performance of a data processing system |
October 2, 2007 |
| An improved system and method for completing performance analysis for a target system is disclosed. According to the current invention, different types of configurations files are created, each to describe one or more respective aspects and/or portions of the target system. Each of these |
| 7260677 |
Programmable system and method for accessing a shared memory |
August 21, 2007 |
| A memory control system and method is disclosed. In one embodiment, a first memory is coupled to one or more additional memories. The first memory receives requests for data that are completed by retrieving the data from the first memory and/or the one or more additional memories. Th |
| 7213109 |
System and method for providing speculative ownership of cached data based on history tracking |
May 1, 2007 |
| A system and method for managing memory data is provided. Data stored within a main memory may be requested by multiple requesters that may include one or more cache memories. When the data is provided by the main memory to a requester, it will be provided in a state that is based on |
| 7167955 |
System and method for testing and initializing directory store memory |
January 23, 2007 |
| A system and method for testing and/or initializing a Directory Store in a directory-based coherent memory. In one illustrative embodiment, the directory-based coherent memory includes a Main Store for storing a number of data entries, a Directory Store for storing the directory state |
| 7047322 |
System and method for performing conflict resolution and flow control in a multiprocessor system |
May 16, 2006 |
| The current invention provides a system and method for managing requests from one or more requesters to one or more resources. These requests, which may be any of multiple request types, are prioritized using one or more threshold values. Each threshold value is associated with one or |
| 6981106 |
System and method for accelerating ownership within a directory-based memory system |
December 27, 2005 |
| The current invention provides a system and method for managing data stored within a main storage device such as a main memory. In one embodiment, multiple requesters are coupled to the main storage device to store copies of ones of the data signals. A directory is coupled to the main st |
| 6973548 |
Data acceleration mechanism for a multiprocessor shared memory system |
December 6, 2005 |
| A dual-channel memory system and accompanying coherency mechanism is disclosed. The memory includes both a request and a response channel. The memory provides data to a requester such as an instruction processor via the response channel. If this data is provided for update purposes, othe |
| 6868482 |
Method and apparatus for parallel store-in second level caching |
March 15, 2005 |
| Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the dual system with the first-level and second-level caches being globally addressable to all |
| 6799252 |
High-performance modular memory system with crossbar connections |
September 28, 2004 |
| A modular, expandable, multi-port main memory system that includes multiple point-to-point switch interconnections and a highly-parallel data path structure that allows multiple memory operations to occur simultaneously. The main memory system includes an expandable number of modular Mem |
| 6728835 |
Leaky cache mechanism |
April 27, 2004 |
| An apparatus for and method of improving the efficiency of a level two cache memory. In response to a level one cache miss, a request is made to the level two cache. A signal sent with the request identifies when the requester does not anticipate a near term subsequent use for the reques |
| 6594785 |
System and method for fault handling and recovery in a multi-processing system having hardware r |
July 15, 2003 |
| Poisoning of specific memory locations as a process when a part of a multiprocessor computer system becomes faulty leads to ability to isolate specific data owned by individual failing units even in a shared memory area. Also continuous processing by non-failing units is allowable. A |
| 6587931 |
Directory-based cache coherency system supporting multiple instruction processor and input/outpu |
July 1, 2003 |
| A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/O) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more |
| 6480927 |
High-performance modular memory system with crossbar connections |
November 12, 2002 |
| A modular, expandable, multi-port main memory system that includes multiple point-to-point switch interconnections and a highly-parallel data path structure that allows multiple memory operations to occur simultaneously. The main memory system includes an expandable number of modular Mem |
| 6477620 |
Cache-level return data by-pass system for a hierarchical memory |
November 5, 2002 |
| A data by-pass system for a hierarchical, multi-level, memory is disclosed. The by-pass system provides by-pass interfaces between storage devices located at predetermined levels within the memory hierarchy. The hierarchical memory system of the preferred embodiment includes a main m |
| 6457101 |
System and method for providing the speculative return of cached data within a hierarchical memo |
September 24, 2002 |
| A hierarchical memory structure includes a directory-based main memory coupled to multiple first storage devices, each to store data signals retrieved from the main memory. Ones of the first storage devices are further respectively coupled to second storage devices, each to store data |
| 6453276 |
Method and apparatus for efficiently generating test input for a logic simulator |
September 17, 2002 |
| A method and apparatus for generating test input for a logic simulator by providing a template that allows a test designer to more efficiently enter the desired test conditions. The template is preferably arranged to facilitate the definition of test cases, and in particular, parallel ty |
| 6438659 |
Directory based cache coherency system supporting multiple instruction processor and input/outpu |
August 20, 2002 |
| A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/0) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more |
| 6434641 |
System for reducing the number of requests presented to a main memory in a memory storage system |
August 13, 2002 |
| A memory request management system for use with a memory system employing a directory-based cache coherency scheme is disclosed. The memory system includes a main memory coupled to receive requests from multiple cache memories. Directory-based logic is used to determine that some request |
| 6415364 |
High-speed memory storage unit for a multiprocessor system having integrated directory and data |
July 2, 2002 |
| A high-speed memory system is disclosed for use in supporting a directory-based cache coherency protocol. The memory system includes at least one data system for storing data, and a corresponding directory system for storing the corresponding cache coherency information. Each data st |
| 6381715 |
System and method for performing parallel initialization and testing of multiple memory banks an |
April 30, 2002 |
| A system and method for testing and initializing a memory including multiple memory banks or a memory module partitioned into logical memory units. A plurality of memory exerciser testers are provided, one for each of the plurality of memory banks. Each of the memory exerciser testers |
| 6356991 |
Programmable address translation system |
March 12, 2002 |
| A programmable address translation system for a modular main memory is provided. The system is implemented using one or more General Register Arrays (GRAs), wherein each GRA performs logical-to-physical address translation for a predetermined address range within the system. Predeter |
| 6336088 |
Method and apparatus for synchronizing independently executing test lists for design verificatio |
January 1, 2002 |
| Method and apparatus for synchronizing the execution of the two or more test lists at desired synchronization points, while allowing the test lists to execute in a non-deterministic manner between the synchronization points is disclosed. A test driver is provided for executing each test |
| 6279098 |
Method of and apparatus for serial dynamic system partitioning |
August 21, 2001 |
| A method and apparatus for providing for serially transmitting partitioning information between system partitions, and between system partitions and the corresponding data processing resources. Serial transmission may allow the partitioning information to be transmitted using a single I/ |
| 6226716 |
Test driver for use in validating a circuit design |
May 1, 2001 |
| A test driver for use in validating an electronic circuit design is disclosed. The test driver not only provides stimulus and verifies the response of a circuit design, but also responds appropriately to requests provided by the circuit design. The test driver may also modify a selected |
| 6199135 |
Source synchronous transfer scheme for a high speed memory interface |
March 6, 2001 |
| Data transfer scheme wherein data transfer rates can be effectively doubled with no increase in the clock speed of the interface. This is accomplished by allowing more than one data transfer to occur on a single clock cycle. This transfer scheme increases the transfer rate of the interfa |
| 6189078 |
System and method for increasing data transfer throughput for cache purge transactions using mul |
February 13, 2001 |
| A system and method for reducing data transfer delays in a transaction processing system is provided. The system includes a plurality of devices each having an associated local memory, and a supervisory memory module having a main storage module for storing data segments and a directory |
| 6167489 |
System and method for bypassing supervisory memory intervention for data transfers between devic |
December 26, 2000 |
| A system and method for providing direct transfers of data segments between devices having local memories without the need for first transferring the data to a central supervisory memory to maintain cache coherency. Direct data transfers are performed from a first local memory of a first |
| 6122711 |
Method of and apparatus for store-in second level cache flush |
September 19, 2000 |
| Flush apparatus for a dual multi-processing system. Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the dual system with the first-level and seco |
| 6055607 |
Interface queue with bypassing capability for main storage unit |
April 25, 2000 |
| A method of interfacing multiple requests using a request hold register, a multiplexer and a snapshot register with multiple requests directed into both the request hold register and a multiplexer which prevents forwarding the requests to the snapshot register if the snapshot register is |
| 6052760 |
Computer system including plural caches and utilizing access history or patterns to determine da |
April 18, 2000 |
| A system and method for enabling a multiprocessor system employing a memory hierarchy to identify data units or locations being used as software locks. The memory hierarchy comprises a main memory having a plurality of data units, a plurality of caches that operate independently of each |
| 6049845 |
System and method for providing speculative arbitration for transferring data |
April 11, 2000 |
| A system and method for optimizing the amount of time it takes for a requestor (device) to receive data from a memory storage unit in a multi-requestor bus environment. The present invention provides a unidirectional response signal, referred to as an early warning signal, sent from |
| 6014709 |
Message flow protocol for avoiding deadlocks |
January 11, 2000 |
| System and method for controlling the flow of messages in a computer system to minimize congestion and prevent deadlocks in communications. The computer system includes a main memory, a plurality of crossbar switches, a plurality of third level caches, and a plurality of input/output |
| 5960455 |
Scalable cross bar type storage controller |
September 28, 1999 |
| Method and apparatus for a computer system to efficiently operate with multiple instruction processors and input/output subsystem in a symmetrical multi-processing environment. The computer system uses a new storage controller having a high performance interconnect scheme that scales |
| 5946710 |
Selectable two-way, four-way double cache interleave scheme |
August 31, 1999 |
| Method and apparatus for maximizing cache memory throughput in a system where a plurality of requesters may contend for access to a same memory simultaneously. The memory utilizes an interleaved addressing scheme wherein each memory segment is associated with a separate queuing struc |
| 5875462 |
Multi-processor data processing system with multiple second level caches mapable to all of addre |
February 23, 1999 |
| A cache architecture for a multiprocessor data processing system. The cache architecture includes multiple first-level caches, two second-level caches, and main storage that is addressable by each of the processors. Each first-level cache is dedicated to a respective one of the processor |
| 5875201 |
Second level cache having instruction cache parity error control |
February 23, 1999 |
| Method and apparatus for detecting and correcting memory storage data errors in a system utilizing parity error detection. An error detected in the memory storage device results in a parity error being reported, thereby causing the corresponding address location to be deactivated. Once |
| 5860093 |
Reduced instruction processor/storage controller interface |
January 12, 1999 |
| Method and apparatus for reducing address/function transfer pins in a system where cache memories in a system controller are accessed by a number of instruction processors. The reduction of pins is obtained by using two data transfers. The increase in data addressing time, which woul |
| 5832304 |
Memory queue with adjustable priority and conflict detection |
November 3, 1998 |
| An improved memory request storage and allocation system using parallel queues to retain different categories of memory requests until they can be acted on by the main memory. Memory requests in the parallel queues are allowed to access the main memory according to a queue priority schem |
| 5822766 |
Main memory interface for high speed data transfer |
October 13, 1998 |
| An apparatus and method for transferring data sets between a storage controller and a number of daisy chained main memories on separate circuit elements at high speed. Each main memory has coupled control logic which receives a data set from the storage controller, latches and retransmit |
| 5678026 |
Multi-processor data processing system with control for granting multiple storage locks in paral |
October 14, 1997 |
| A storage lock apparatus for a multiprocessor data processing system. The storage lock apparatus includes control for granting locks to different selectable portions of storage in parallel. In addition, acknowledgment from a remote lock controller is not required for a processor to obtai |
| 5625892 |
Dynamic power regulator for controlling memory power consumption |
April 29, 1997 |
| A dynamic power consumption reduction apparatus for reducing power consumption by temporarily delaying multiple data transfer interfaces. Data transfer interfaces are only delayed in rare circumstances where an exceptionally high number of data transfers are occurring for a period of |
| 5617375 |
Dayclock carry and compare tree |
April 1, 1997 |
| An apparatus for and method of efficiently providing a modular dayclock within a data processing system. This is accomplished by dividing the dayclock hardware into a number of dayclock modules configured to operate in a bit serial fashion. This allows the dayclock to accommodate a varie |
