| Patent Number |
Title Of Patent |
Date Issued |
| 7607071 |
Error correction using iterating generation of data syndrome |
October 20, 2009 |
| An embodiment of the present invention is a technique to perform error correction using a trial-and-error method. A syndrome generator provides a generation of a data syndrome of a data word modified according to a selection of at least one of error correcting parameters. The data word |
| 7024533 |
Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic init |
April 4, 2006 |
| A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory |
| 6636955 |
Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic init |
October 21, 2003 |
| A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory |
| 5303358 |
Prefix instruction for modification of a subsequent instruction |
April 12, 1994 |
| A method and apparatus for instruction prefixing selectively reconfigures certain of the instructions in the microprocessor's instruction set so as to alter the nature of the operation performed by the instruction and/or the designation of operand or result locations accessed by the oper |
| 5187791 |
Microprocessor with improved interrupt response with data saving dependent upon processor status |
February 16, 1993 |
| A method for reducing interrupt processing overhead is applied in situations when it is not necessary to preserve processor state information. A flag is provided to indicate whether or not the processor is available. Upon recognition of an interrupt, an interrupt vector address is co |
| 5095526 |
Microprocessor with improved interrupt response with interrupt data saving dependent upon proces |
March 10, 1992 |
| A method for reducing interrupt processing overhead is applied in situations when it is not necessary to preserve processor state information. A flag is provided to indicate whether or not the processor is available. Upon recognition of an interrupt, an interrupt vector address is co |
| 5051896 |
Apparatus and method for nullifying delayed slot instructions in a pipelined computer system |
September 24, 1991 |
| In a computing system which has memory and an instruction pipeline, a method and apparatus allows for nullification of a second instruction responsive to the state of a nullification field in a first instruction executed prior to the second instruction. After the first instruction is |
| 5001662 |
Method and apparatus for multi-gauge computation |
March 19, 1991 |
| Methods and apparatus are provided for performing multi-gauge arithmetic operations in a microprocessor CPU. Special purpose instructions facilitate parallel processing of individual bytes or half words of data words without requiring that the processor's mode be separately controlle |
| 4873627 |
Method and means for conditional storing of data in a reduced instruction set computer |
October 10, 1989 |
| In a computer device in accordance with the preferred embodiment of the invention, an instruction set which uses a two-instruction sequence to store the result of a comparison is provided. The two-instruction sequence, which uses no branch instructions, does not need to wait for cond |
| 4755966 |
Bidirectional branch prediction and optimization |
July 5, 1988 |
| A method and apparatus for efficient branching within a central processing unit with overlapped fetch and execute cycles which optimizes the efficient fetching of instructions. |
| 4747046 |
Mechanism for comparing two registers and storing the result in a general purpose register witho |
May 24, 1988 |
| In a computer device, an instruction set which uses a two-instruction sequence to store the result of a comparison is provided. The two-instruction sequence, which uses no branch instructions, does not need to wait for condition resolution before storing conditional results. Addition |
| 4739471 |
Method and means for moving bytes in a reduced instruction set computer |
April 19, 1988 |
| A basic instruction for moving a string of bytes in a word has been devised. Because the operations in the instruction are basic, very few variations are necessary to accommodate diversity of lengths and variables. These operations are imbedded in a single code sequence; the compiler |
| 4722050 |
Method and apparatus for facilitating instruction processing of a digital computer |
January 26, 1988 |
| A computer having a cache memory and a main memory is provided with a transformation unit between the main memory and the cache memory so that at least a portion of an information unit retrieved from the main memory may be transformed during retrieval of the information (fetch) from a ma |
