| Patent Number |
Title Of Patent |
Date Issued |
| 6014728 |
Organization of an integrated cache unit for flexible usage in supporting multiprocessor operati |
January 11, 2000 |
| A computer system having a cache memory subsystem which allows flexible setting of caching policies on a page basis and a line basis. A cache block status field is provided for each cache block to indicate the cache block's state, such as shared or exclusive. The cache block status field |
| 5627992 |
Organization of an integrated cache unit for flexible usage in supporting microprocessor operati |
May 6, 1997 |
| A computer system having a cache memory subsystem which allows flexible setting of caching policies on a page basis and a line basis. A cache block status field is provided for each cache block to indicate the cache block's state, such as shared or exclusive. The cache block status field |
| 5185878 |
Programmable cache memory as well as system incorporating same and method of operating programma |
February 9, 1993 |
| Methods and apparatus are disclosed for realizing an integrated cache unit (ICU) comprising both a cache memory and a cache controller on a single chip. The novel ICU is capable of being programmed, supports high speed data and instruction processing applications in both Reduced Instruct |
| 5136691 |
Methods and apparatus for caching interlock variables in an integrated cache memory |
August 4, 1992 |
| Methods and apparatus are disclosed for supporting the caching of interlock variables in cache memory units employed in multiprocessor and/or multitasking environments. The preferred embodiment of the invention includes methods and apparatus for selectively treating interlock variabl |
| 5025366 |
Organization of an integrated cache unit for flexible usage in cache system design |
June 18, 1991 |
| Methods and apparatus are disclosed for realizing an integrated cache unit which may be flexibly used for cache system design. The preferred embodiment of the invention comprises both a cache memory and a cache controller on a single chip. In accordance with an alternative embodiment |
| 4926323 |
Streamlined instruction processor |
May 15, 1990 |
| A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching |
| 4851990 |
High performance processor interface between a single chip processor and off chip memory means h |
July 25, 1989 |
| Methods and apparatus for realizing a high performance interface between a processor, constituting part of a reduced instruction set computer (RISC) system, and a set of devices, including memory means. According to the invention, the interface includes three independent buses. A shared |
| 4761567 |
Clock scheme for VLSI systems |
August 2, 1988 |
| An integrated circuit includes an input clock generator circuit responsive to an external TTL level clock signal for generating an internal CMOS level system clock signal for its own use and for use by other integrated circuits. The integrated circuit also includes an internal clock gene |
