| Patent Number |
Title Of Patent |
Date Issued |
| 4412303 |
Array processor architecture |
October 25, 1983 |
| A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection net |
| 4385371 |
Approximate content addressable file system |
May 24, 1983 |
| In an approximate content addressable storage system data words are stored in a two dimensional storage array with each data character therein stored in a particularly associated storage row and each data word individually and sequentially character-by-character stored column-by-column. |
| 4365292 |
Array processor architecture connection network |
December 21, 1982 |
| A connection network is disclosed for use between a parallel array of processors and a parallel array of memory modules for establishing non-conflicting data communications paths between requested memory modules and requesting processors. The connection network includes a plurality of |
| 4344134 |
Partitionable parallel processor |
August 10, 1982 |
| In a parallel processing array wherein each processor therein issues a ready signal to signify that it is ready to begin a parallel processing task and initiates the task upon receipt of an initiate signal the parallel processing array is rendered partitionable into parallel processi |
| 4223391 |
Parallel access alignment network with barrel switch implementation for d-ordered vector element |
September 16, 1980 |
| An alignment network between N parallel data input ports and N parallel data outputs includes a first and a second barrel switch. The first barrel switch fed by the N parallel input ports shifts the N outputs thereof and in turn feeds the N-1 input data paths of the second barrel switch |
| 4162534 |
Parallel alignment network for d-ordered vector elements |
July 24, 1979 |
| An alignment network having N parallel data inputs includes log.sub.2 N rounded up to the nearest integer of levels, each level therein including N selection gates for providing selectively direct through data flow and incrementally shifted or transposed data flow. The selectable shift a |
