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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Bae; Geum-Jong
Address:
Kyunggi-do, KR
No. of patents:
9
Patents:












Patent Number Title Of Patent Date Issued
6917085 Semiconductor transistor using L-shaped spacer July 12, 2005
The present invention provides a semiconductor transistor using an L-shaped spacer. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped
6881650 Method for forming SOI substrate April 19, 2005
A method for forming SOI substrates including a SOI layer containing germanium and a strained silicon layer disposed on the SOI layer, comprises forming a relaxed silicon-germanium layer on a first silicon substrate using an epitaxial growth method, and forming a porous silicon-germa
6881621 Method of fabricating SOI substrate having an etch stop layer, and method of fabricating SOI int April 19, 2005
A method of fabricating a SOI substrate includes sequentially forming a first semiconductor layer, which may be either a porous semiconductor layer or a bubble layer, a second semiconductor layer and a buried oxide layer on a front surface of a semiconductor substrate, forming an etch
6794306 Semiconductor device having gate all around type transistor and method of forming the same September 21, 2004
A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon ge
6716689 MOS transistor having a T-shaped gate electrode and method for fabricating the same April 6, 2004
A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface
6670677 SOI substrate having an etch stop layer and an SOI integrated circuit fabricated thereon December 30, 2003
A SOI substrate having an etch stopping layer, a SOI integrated circuit fabricated on the SOI substrate, and a method of fabricating both are provided. The SOI substrate includes a supporting substrate, an etch stopping layer staked on the supporting substrate, a buried oxide layer a
6605847 Semiconductor device having gate all around type transistor and method of forming the same August 12, 2003
A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon ge
6541822 Method of manufacturing an SOI type semiconductor that can restrain floating body effect April 1, 2003
A method of forming a SOI type semiconductor device comprises forming a first trench in a SOI layer forming a portion of an isolation layer region between an element region and a ground region by etching the SOI layer of a SOI type substrate using an etch stop layer pattern as an etch ma
6524902 Method of manufacturing CMOS semiconductor device February 25, 2003
In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMO










 
 
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