| Patent Number |
Title Of Patent |
Date Issued |
| 7558944 |
Microcomputer |
July 7, 2009 |
| A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from |
| 7505329 |
Data line disturbance free memory block divided flash memory and microcomputer having flash memo |
March 17, 2009 |
| A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units |
| 7363466 |
Microcomputer |
April 22, 2008 |
| A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from |
| 7295476 |
Data line disturbance free memory block divided flash memory and microcomputer having flash memo |
November 13, 2007 |
| A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units |
| 7184321 |
Data line disturbance free memory block divided flash memory and microcomputer having flash memo |
February 27, 2007 |
| A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units |
| 7069423 |
Microcomputer |
June 27, 2006 |
| A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from |
| 6999350 |
Data line disturbance free memory block divided flash memory and microcomputer having flash memo |
February 14, 2006 |
| A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units |
| 6996700 |
Microcomputer and dividing circuit |
February 7, 2006 |
| Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decod |
| 6889240 |
Data processing device having a central processing unit and digital signal processing unit |
May 3, 2005 |
| In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in |
| 6804152 |
Method for manufacturing a printed board on which a semiconductor device having two modes is mou |
October 12, 2004 |
| A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of p |
| 6690603 |
Microcomputer including a flash memory that is two-way programmable |
February 10, 2004 |
| A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of p |
| 6668266 |
Data processing device having a central processing unit and digital signal processing unit |
December 23, 2003 |
| In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in |
| 6493271 |
Data line disturbance free memory block divided flash memory and microcomputer having flash memo |
December 10, 2002 |
| A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of p |
| 6434690 |
Microprocessor having a DSP and a CPU and a decoder discriminating between DSP-type instructions |
August 13, 2002 |
| A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the |
| 6414878 |
Data line disturbance free memory block divided flash memory and microcomputer having flash memo |
July 2, 2002 |
| A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of |
| 6405302 |
Microcomputer |
June 11, 2002 |
| A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the |
| 6400609 |
Data line disturbance free memory block divided flash memory and microcomputer having flash memo |
June 4, 2002 |
| A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of |
| 6343357 |
Microcomputer and dividing circuit |
January 29, 2002 |
| A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed l |
| 6335879 |
Method of erasing and programming a flash memory in a single-chip microcomputer having a process |
January 1, 2002 |
| A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of |
| 6272620 |
Central processing unit having instruction queue of 32-bit length fetching two instructions of 1 |
August 7, 2001 |
| A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed l |
| 6253308 |
Microcomputer having variable bit width area for displacement and circuit for handling immediate |
June 26, 2001 |
| A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed l |
| 6205535 |
Branch instruction having different field lengths for unconditional and conditional displacement |
March 20, 2001 |
| A branch instruction format has different respective field lengths for conditional branch instructions and unconditional branch instructions. A conditional branch instruction has a first bit length and a first area for a displacement designating an address to be jumped, wherein the first |
| 6181598 |
Data line disturbance free memory block divided flash memory and microcomputer having flash memo |
January 30, 2001 |
| A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of |
| 6166953 |
Data line disturbance free memory block divided flash memory and microcomputer having flash memo |
December 26, 2000 |
| A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of |
| 6131154 |
Microcomputer having variable bit width area for displacement |
October 10, 2000 |
| Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding |
| 6130836 |
Semiconductor IC device having a control register for designating memory blocks for erasure |
October 10, 2000 |
| A semiconductor integrated circuit device having a processing unit and a memory which stores data to be processed by the processing unit and which provides data to the processing unit through the data bus in response to accessing instructions from the processing unit through the address |
| 6122724 |
Central processing unit having instruction queue of 32-bit length fetching two instructions of 1 |
September 19, 2000 |
| A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed l |
| 6064593 |
Semiconductor integrated circuit device having an electrically erasable and programmable nonvola |
May 16, 2000 |
| A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of |
| 6026020 |
Data line disturbance free memory block divided flash memory and microcomputer having flash memo |
February 15, 2000 |
| A single chip semiconductor integrated circuit device having a central processing unit (CPU) and a flash memory which stores data to be processed by the CPU and which provides data to the CPU through the data bus in response to accessing instructions from the CPU through the address bus. |
| 5991545 |
Microcomputer having variable bit width area for displacement and circuit for handling immediate |
November 23, 1999 |
| Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding |
| 5969976 |
Division circuit and the division method thereof |
October 19, 1999 |
| A division method and circuit performs a division for signed data by adding or subtracting a divisor to or from the dividend or the partial remainder from the division, according to the sign of the divisor or the dividend and the partial remainder to acquire a new partial remainder. The |
| 5884092 |
System for maintaining fixed-point data alignment within a combination CPU and DSP system |
March 16, 1999 |
| In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chippthis invention |
| 5867726 |
Microcomputer |
February 2, 1999 |
| A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the |
| 5768194 |
Data line disturbance free memory block divided flash memory and microcomputer having flash memo |
June 16, 1998 |
| A single chip semiconductor integrated circuit device having a central processing unit (CPU) and a flash memory which stores data to be processed by the CPU and which provides data to the CPU through the data bus in response to accessing instructions from the CPU through the address bus. |
| 5682545 |
Microcomputer having 16 bit fixed length instruction format |
October 28, 1997 |
| Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding |
| 5666510 |
Data processing device having an expandable address space |
September 9, 1997 |
| A CPU has an upper compatibility with a low-order CPU to expand a continuously usable address space relatively. For latching data information, registers are constructed for being an address register with a bit number larger than the address bit number of a low-order CPU. The data inf |
| 5581503 |
Data line disturbance free memory block divided flash memory and microcomputer having flash memo |
December 3, 1996 |
| An electrically rewritable flash memory device which has a memory cell array arranged in rows and columns of memory cells and which is divided into a plurality of memory blocks having different memory capacities. Each memory block having one or more rows of memory cells. A common voltage |
