| Patent Number |
Title Of Patent |
Date Issued |
| 7392354 |
Multi-queue FIFO memory devices that support a backed-off standard mode of operation and methods |
June 24, 2008 |
| Multi-Q FIFO memory devices are configured to support a backed-off standard (BOS) mode of operation. This mode of operation enables automatic re-reading of at least one data word previously read from a first queue in the FIFO memory chip during a first FIFO read operation, in respons |
| 7269700 |
Status bus accessing only available quadrants during loop mode operation in a multi-queue first- |
September 11, 2007 |
| A flag logic circuit is provided for use in a multi-queue memory device having a plurality of queues. A first stage memory stores a flag value for each of the queues in the multi-queue memory device. Flag values are routed from the first stage memory to a flag status bus having a width N |
| 7257687 |
Synchronization of active flag and status bus flags in a multi-queue first-in first-out memory s |
August 14, 2007 |
| A flag logic circuit includes a first comparator configured to generate a first flag value associated with an active read queue of a multi-queue memory device, and a second comparator configured to generate a second flag value associated with an active write queue of the multi-queue |
| 7246300 |
Sequential flow-control and FIFO memory devices having error detection and correction capability |
July 17, 2007 |
| FIFO memory devices include a multi-port cache memory device configured to generate a data word along with a plurality of diagnostic bits. These diagnostics bits encode an error correction status of the data word and a path traversal status of the data word through the FIFO memory device |
| 7209983 |
Sequential flow-control and FIFO memory devices that are depth expandable in standard mode opera |
April 24, 2007 |
| FIFO memory devices are configured to support a pair of hybrid operating modes that enable the FIFO memory device to be depth-expandable with other FIFO memory devices in a collective standard mode of operation. The pair of hybrid operating modes including a first hybrid mode that su |
| 7154327 |
Self-timed multiple blanking for noise suppression during flag generation in a multi-queue first |
December 26, 2006 |
| A write counter provides a write count value synchronized with a write clock signal. A read counter provides a read count value synchronized with a read clock signal. The read and write count values are routed through logic, which introduces noise to these values. A first delay circu |
| 7099231 |
Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memo |
August 29, 2006 |
| A multi-queue memory system includes first and second memory blocks. The first memory block includes a first array of memory cells, a first sense amplifier circuit and a second sense amplifier circuit. The second memory block includes a second array of memory cells, a third sense amplifi |
| 7093047 |
Integrated circuit memory devices having clock signal arbitration circuits therein and methods o |
August 15, 2006 |
| A clock signal arbitration method includes arbitrating between first and second request signals generated in respective first and second clock domains that are asynchronously timed relative to each other, to obtain first arbitration results. These first arbitration results identify a |
| 7082071 |
Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadca |
July 25, 2006 |
| An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and |
| 7076610 |
FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latenc |
July 11, 2006 |
| An integrated circuit memory device includes a quad-port cache memory device and a higher capacity supplemental memory device. These memory devices operate collectively as a high speed FIFO having fast fall through capability and extended data capacity. The FIFO does not require comp |
| 7042792 |
Multi-port memory cells for use in FIFO applications that support data transfers between cache a |
May 9, 2006 |
| A multi-port memory cell includes a first SRAM element having a first pair of access transistors electrically coupled to a pair of FIFO write bit lines. A second dual-port SRAM element is also provided. This second dual-port SRAM element has a second pair of access transistors electr |
| 6874064 |
FIFO memory devices having multi-port cache and extended capacity memory devices therein with re |
March 29, 2005 |
| A FIFO memory device includes a multi-port cache memory and an extended capacity memory (e.g., SRAM). The multi-port cache memory includes a data input port, a data output port, a first memory port that is configured to pass write data to the extended capacity memory during memory write |
| 6754777 |
FIFO memory devices and methods of operating FIFO memory devices having multi-port cache memory |
June 22, 2004 |
| A FIFO memory device includes an embedded memory array having a write port and a read port and a quad-port cache memory device. The cache memory device has a unidirectional data input port, a unidirectional data output port, a first embedded memory port that is electrically coupled to th |
| 6546461 |
Multi-port cache memory devices and FIFO memory devices having multi-port cache memory devices t |
April 8, 2003 |
| A FIFO memory device includes an embedded memory array having a write port and a read port and a quad-port cache memory device. The cache memory device has a unidirectional data input port, a unidirectional data output port, a first embedded memory port that is electrically coupled to th |
