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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Asano; Tetsuro
Address:
Ora-gun, JP
No. of patents:
12
Patents:












Patent Number Title Of Patent Date Issued
7732868 Semiconductor device June 8, 2010
A protecting element, comprising a first n+-type region, an insulating region, and a second n+-type region, is connected in parallel between two terminals of an FET. Since discharge across the first and second n+ regions is enabled, electrostatic energy that reaches the operating reg
7358788 Compound semiconductor switching circuit device April 15, 2008
Protecting elements are respectively connected between a control terminal Ctl and a ground terminal GND of a logic circuit L, between a point Cp and a ground terminal GND, and between a power supply terminal V.sub.DD and a ground terminal GND thereof. With this, an E-FET, constituting an
7005688 Semiconductor device with impurity layer to prevent depletion layer expansion February 28, 2006
A semiconductor switching device includes a plurality of metal layers. At least one of the metal layers forming a Schottky junction with a semi-insulating substrate or an insulating layer on a substrate. The device also includes an impurity diffusion region, and a high-concentration
6894371 Semiconductor device May 17, 2005
In a case of a semiconductor chip having an electrode pad to be wire-bonded to a header, securing of a fixing region is difficult since the spread of an Ag paste cannot be controlled, therefore, there has existed a problem such that stable manufacturing could not be carried out. Also, th
6891267 Semiconductor switching circuit device May 10, 2005
A semiconductor switching circuit device includes a field effect transistor having a source electrode, a gate electrode and a drain electrode, a first electrode pad connected to the source electrode or the drain electrode, and a second electrode pad connected to the source electrode or t
6867115 Compound semiconductor device March 15, 2005
The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 .mu.m for obtaining a proper
6833608 Semiconductor device and packaging system therefore December 21, 2004
Two different switches with two different signal input schemes are fabricated by mounting the same semiconductor chip on the same lead pattern. Two of the leads of the lead pattern provides space enough for wire-bonding connection to corresponding electrode pads on the semiconductor
6737890 Switching circuit device May 18, 2004
A switching circuit device has a first FET and a second FET, and operates with single control terminal. The device also has a common input terminal connected to the drain or source electrode of the two FETs, a first output terminal and a second output terminal connected to the source or
6657266 Semiconductor switching device December 2, 2003
A switching circuit device has a first FET and a second FET, and operates with single control terminal. The device also has a common input terminal connected to the drain or source electrode of the two FETs, a first output terminal and a second output terminal connected to the source or
6627956 Semiconductor switching device September 30, 2003
A semiconductor switching device of mirror logic includes two FETs having a gate width of 600 .mu.m, a common input terminal, two control terminal and two output terminals. The resistors connecting the control terminals and the gate electrodes of FETs are placed underneath a pad metal la
6573529 Semiconductor switching device June 3, 2003
A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 .mu.m and a signal receiving FET has a gate width of 400 .mu.m. A resistor connecting a gate
5837570 Heterostructure semiconductor device and method of fabricating same November 17, 1998
A heterostructure semiconductor device such as a GaAs MESFET has an n-type GaAs layer disposed as a channel region in a substrate, a gate electrode disposed on the n-type GaAs layer in direct contact therewith, source and drain electrodes disposed on the n-type GaAs layer, and a GaInP la










 
 
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