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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Asakura; Mikio
Address:
Hyogo, JP
No. of patents:
81
Patents:


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Patent Number Title Of Patent Date Issued
6859403 Semiconductor memory device capable of overcoming refresh disturb February 22, 2005
Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The secon
6762967 Semiconductor memory device having a circuit for fast operation July 13, 2004
A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of th
6690241 Ring oscillator having variable capacitance circuits for frequency adjustment February 10, 2004
A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the freq
6687174 Semiconductor memory device capable of switching output data width February 3, 2004
In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO<0> to
6614713 Semiconductor memory device having a circuit for fast operation September 2, 2003
A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of th
6551846 Semiconductor memory device capable of correctly and surely effecting voltage stress acceleratio April 22, 2003
A test signal generating circuit generates internal test control signals from a small number of signals supplied via an address terminal in a test mode operation. According to the test control signals, the values of internal row address signal bits from an address buffer are set, while a
6535412 Semiconductor memory device capable of switching output data width March 18, 2003
In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO<0> to
6504744 Semiconductor memory device with memory test circuit January 7, 2003
A semiconductor memory device includes a plurality of array blocks including word lines, memory cells, bit lines, dummy word lines and transistors. In a test mode, rather than a word line a dummy word line is selected. Selectively turning on either one of the transistors allows a bit
6490221 Semiconductor memory device with low power consumption December 3, 2002
A semiconductor memory device includes: a memory cell region constructed of blocks and a memory cell region constructed of blocks. The blocks and the blocks are continuously disposed. A block decoder outputs block select signals to the respective blocks. As a result, power consumption of
6477105 Semiconductor memory device with a hierarchical word line configuration capable of preventing le November 5, 2002
Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.
6469327 Semiconductor device with efficiently arranged pads October 22, 2002
Pads are alignedly arranged in a central region of a semiconductor chip and are also arranged at an outer peripheral portion of the central portion of the chip. A pad at the outer peripheral portion is electrically connected to a die pad mounting the chip thereon with an insulative mater
6414883 Semiconductor memory device July 2, 2002
Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The secon
6407942 Semiconductor memory device with a hierarchical word line configuration capable of preventing le June 18, 2002
Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.
6377512 Clock synchronous type semiconductor memory device that can switch word configuration April 23, 2002
Data buses are arranged in a one-to-one correspondence to pads. These data buses are arranged in common to a plurality of memory arrays. A read data driver is rendered active selectively according to a word configuration to switch equivalently the connection between a memory array and a
6341089 Semiconductor memory device allowing effective detection of leak failure January 22, 2002
An internal signal RAS generated in accordance with command input and indicating activation of a row is delayed in accordance with a dock signal int.CLKI, and thereby a sense amplifier activating signal is issued. A time from activation of a word line by a signal WLT to activation of a
6335887 Semiconductor memory device allowing switching of word configuration January 1, 2002
The semiconductor memory device has a word configuration determination signal generating circuit including a plurality of generating circuits, each of which is formed of two clocked inverters and two inverters. In a normal operation mode, a test mode signal TX4 is inactivated and a word
6330173 Semiconductor integrated circuit comprising step-up voltage generation circuit December 11, 2001
A VPP generation circuit included in the inventive semiconductor integrated circuit includes a VPP dividing circuit dividing a step-up voltage VPP, a VDDA dividing circuit dividing an array voltage VDDA supplied to a memory cell array area, a VREFD generation circuit generating a referen
6327198 Semiconductor memory device having a test mode setting circuit December 4, 2001
A semiconductor memory device according to the present invention includes: a test mode setting circuit capable of serially setting a plurality of test modes in accordance with an external signal; a voltage generating circuit; a column related control circuit; a row related control circui
6301169 Semiconductor memory device with IO compression test mode October 9, 2001
In a set of memory cells selected by one column select line, a memory cell of at least 1 bit is connected to an internal data line that is different from the internal data line to which another memory cell in the same set is connected. An internal data line pair is connected to a data te
6295238 Semiconductor memory device having a circuit for fast operation September 25, 2001
A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of th
6288956 Semiconductor device having test function September 11, 2001
A semiconductor device according to the present invention includes a plurality of test mode circuits. Each test mode circuit includes a plurality of decode circuits decoding an input signal and a plurality of latch circuits. Each decode circuit generates a test mode signal. The test
6272055 Semiconductor memory device August 7, 2001
Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The secon
6269038 Semiconductor memory device with test mode decision circuit July 31, 2001
There is provided a test mode decision circuit which in the first WCBR cycle responds to an address key by activating a test mode entry signal and with the test mode entry signal activated in the second WCBR cycle responds to an address key by selectively activating test mode signals. In
6249462 Data output circuit that can drive output data speedily and semiconductor memory device includin June 19, 2001
An output buffer includes a pull up transistor of N type field effect to charge a data output terminal by an external power supply potential Vdd in a high level data output operation, and a pull down transistor of N type field effect to discharge the data output terminal to a ground pote
6207998 Semiconductor device with well of different conductivity types March 27, 2001
An MOS capacitor is provided in the proximity of the boundary between a P well and an N well formed of a bottom N well and an N well. Accordingly, the proximity of the boundary corresponding to the so-called dead space can be used effectively.
6197643 Method for making level converting circuit, internal potential generating circuit and internal p March 6, 2001
The level converting circuit includes a first current cutting circuit, a second current cutting circuit, a level shift circuit and an inverter. The first current cutting circuit includes two PMOS transistors connected to a node having a boosted potential Vpp. The second current cutting c
6166989 Clock synchronous type semiconductor memory device that can switch word configuration December 26, 2000
Data buses are arranged in a one-to-one correspondence to pads. These data buses are arranged in common to a plurality of memory arrays. A read data driver is rendered active selectively according to a word configuration to switch equivalently the connection between a memory array and a
6157588 Semiconductor memory device having hierarchical word line structure December 5, 2000
First and second global input/output lines are twisted between first and second main blocks. First and second SD signal lines in the first main block are respectively arranged adjacent to first and second global input/output lines. First and second SD signal lines in the second main
6064607 Semiconductor memory device with predecoder May 16, 2000
Each of first and second program circuits includes a determination node, first to fourth fuses, first to fourth N channel MOS transistors, and first to fourth supply lines. The first to fourth N channel MOS transistors receive first to fourth row address predecode signals, respective
6064557 Semiconductor device structured to be less susceptible to power supply noise May 16, 2000
A semiconductor device comprises an MOS transistor, as a capacitive element, formed at the surface of a semiconductor substrate. A first power supply interconnection, above the substrate, applies a first power supply potential to the source and drain of the transistor. A second power sup
6061808 Semiconductor memory device having a multibit test mode May 9, 2000
In a predetermined multibit test mode, a multibit test circuit 114 issues determination result data pairs RDM0 and /RDM0 to RDM3 and /RDM3, each of which corresponds to match/mismatch of logics of data read from memory cells selected by one column select line in corresponding one of memo
6054885 Semiconductor device and testing apparatus thereof April 25, 2000
A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the freq
6005294 Method of arranging alignment marks December 21, 1999
A shot region includes a device region for forming a semiconductor device therein and a dicing region used for dicing. A portion of the peripheral edge portion of the shot region is defined by a portion of the peripheral edge portion of the device region. An alignment mark is arranged wi
6003148 Semiconductor memory device allowing repair of a defective memory cell with a redundant circuit December 14, 1999
In a predetermined multibit test mode, a multibit test circuit 114 issues determination result data pairs RDM0 and /RDM0 to RDM3 and /RDM3, each of which corresponds to match/mismatch of logics of data read from memory cells selected by one column select line in corresponding one of memo
5978299 Semiconductor memory device having a voltage lowering circuit of which supplying capability incr November 2, 1999
A semiconductor memory device includes a memory cell array, peripheral circuits including a column decoder for connecting a word line, and a VDC circuit for peripherals, for generating an internal power supply voltage based on an external power supply voltage. VDC circuit for peripherals
5973554 Semiconductor device structured to be less susceptible to power supply noise October 26, 1999
A semiconductor device comprises an MOS transistor, as a capacitive element, formed at the surface of a semiconductor substrate. A first power supply interconnection, above the substrate, applies a first power supply potential to the source and drain of the transistor. A second power sup
5970004 Semiconductor memory device allowing test regardless of spare cell arrangement October 19, 1999
A semiconductor memory device according to the present invention includes a block determining portion determining a difference in arrangement between a normal cell and a spare cell which replaces it, a data scramble controlling circuit generating a scramble ON signal when a normal cell i
5969984 Level converting circuit for converting level of an input signal, internal potential generating October 19, 1999
The level converting circuit includes a first current cutting circuit, a second current cutting circuit, a level shift circuit and an inverter. The first current cutting circuit includes two PMOS transistors connected to a node having a boosted potential Vpp. The second current cutting c
5966045 Semiconductor device having a first stage input unit to which a potential is supplied from exter October 12, 1999
A power supply for supplying a power supply potential to a first stage input buffer circuit of a semiconductor device is changed according to the types of first stage input circuits. For example, an external power supply potential is supplied without change in a value from an external po
5953261 Semiconductor memory device having data input/output circuit of small occupied area capable of h September 14, 1999
Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided
5943273 Semiconductor memory device August 24, 1999
Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The secon
5917766 Semiconductor memory device that can carry out read disturb testing and burn-in testing reliably June 29, 1999
A semiconductor memory device that operates in various modes such as in a normal operation mode and a disturb accelerated test mode in which two word lines are activated simultaneously, includes a boosting power supply circuit, a boosted voltage supply line, and an input terminal connect
5898316 Mode setting circuit of semiconductor device April 27, 1999
Two NAND gates are provided corresponding to each of a plurality of pads. By connecting a mode switching pad to power supply potential or ground potential, one of the two NAND gates provided corresponding to each pad is activated, and the other NAND gate is non-activated. As a result,
5875145 Semiconductor memory device having a voltage lowering circuit of which supplying capability incr February 23, 1999
A semiconductor memory device includes a memory cell array, peripheral circuits including a column decoder for connecting a word line, and a VDC circuit for peripherals, for generating an internal power supply voltage based on an external power supply voltage. VDC circuit for peripherals
5867439 Semiconductor memory device having internal address converting function, whose test and layout a February 2, 1999
In a semiconductor memory device selectively implementing one of a 4K refresh cycle and a 8K refresh cycle, the positions of externally applied address signal bits are switched internally by address switching circuits such that memory cells at the same positions are selected regardless o
5867418 Semiconductor memory device and semiconductor device February 2, 1999
For each of pads for control clock signals and address signals included in a DRAM, an n type well region is provided, and each n type well region is connected to an upper power supply source only by means of a first lower power supply line. Therefore, compared with the conventional devic
5859799 Semiconductor memory device including internal power supply circuit generating a plurality of in January 12, 1999
A plurality of internal power supply voltage generating circuits generate internal power supply voltages. A column select signal at the same voltage level as a first internal power supply voltage applied to a sense amplifier is generated to an I/O gate circuit connecting a bit line pair
5844767 Level converting circuit for converting level of an input signal, internal potential generating December 1, 1998
The level converting circuit includes a first current cutting circuit, a second current cutting circuit, a level shift circuit and an inverter. The first current cutting circuit includes two PMOS transistors connected to a node having a boosted potential Vpp. The second current cutting c
5838627 Arrangement of power supply and data input/output pads in semiconductor memory device November 17, 1998
Data input/output pad portions are arranged corresponding to memory blocks and adjacent to a corresponding memory block in the center region between memory blocks, and memory blocks. Power supply pads are arranged at both ends of the center region. Power supply pad transmits a power supp
5828258 Semiconductor device and testing apparatus thereof October 27, 1998
A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the freq
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