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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Arimoto; Kazutami
Address:
Hyogo, JP
No. of patents:
146
Patents:


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Patent Number Title Of Patent Date Issued
8089819 Semiconductor device and semiconductor signal processing apparatus January 3, 2012
A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where para
7480168 Semiconductor memory device January 20, 2009
Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charg
7248495 Semiconductor memory device July 24, 2007
Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charg
7139208 Refresh-free dynamic semiconductor memory device November 21, 2006
In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected
7102954 Semiconductor integrated circuit device having logic circuit and dynamic random access memory on September 5, 2006
In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is p
7046543 Semiconductor memory device with improved data retention characteristics May 16, 2006
Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charg
6980454 Low-power consumption semiconductor memory device December 27, 2005
A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit li
6925022 Refresh-free dynamic semiconductor memory device August 2, 2005
In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected sta
6909658 Semiconductor memory device with row selection control circuit June 21, 2005
A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation relat
6898137 Semiconductor memory device with high-speed sense amplifier May 24, 2005
In a Vss precharge scheme, dummy cells including a bit line contact, a storage node contact and a third contact connected to a Vccs power supply line are arranged in complementary bit lines. In a waiting state, H level data is written in each dummy cell from the Vccs power supply line. B
6859403 Semiconductor memory device capable of overcoming refresh disturb February 22, 2005
Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The secon
6804164 Low-power consumption semiconductor memory device October 12, 2004
A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit li
6785157 Semiconductor memory device having a memory cell structure of reduced occupying area August 31, 2004
Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charg
6781915 Semiconductor memory device August 24, 2004
Memory cells are arranged such that one-bit data is stored by two-bit memory cells. The cell plate electrode of the memory cell capacitor and the gate electrode of the memory cell transistor are formed in the same manufacturing step. The amplitude of an isolation control signal applied
6744684 Semiconductor memory device with simple refresh control June 1, 2004
A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation relat
6649984 Logic-merged memory November 18, 2003
In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is p
6643208 Semiconductor integrated circuit device having hierarchical power source arrangement November 4, 2003
A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period.
6636454 Low-power consumption semiconductor memory device October 21, 2003
A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit li
6608795 Semiconductor device including memory with reduced current consumption August 19, 2003
When a row active command ACT_CMD is externally input, an internal clock control circuit activates a signal int.CKE, so that an external clock signal ext.CLK is responsively supplied to an internal memory array as signal int.CLK. Thus, clock control is meticulously conducted, whereby a
6573613 Semiconductor memory device having cell plate electrodes allowing independent power supply for e June 3, 2003
A word line and a cell plate electrode line are formed at a common interconnection layer. A redundant replacement unit for a faulty row is set corresponding to the cell plate electrode line. For each redundant replacement unit, a program element is arranged for stopping supply of a c
6525984 Semiconductor integrated circuit device having hierarchical power source arrangement February 25, 2003
A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period.
6507532 Semiconductor memory device having row-related circuit operating at high speed January 14, 2003
A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal
6498396 Semiconductor chip scale package and ball grid array structures December 24, 2002
An external interconnection unit including a pad provided on a semiconductor chip, a bump electrode formed on a main surface of a semiconductor chip for connection with the board, and a connection interconnection for connecting the pad and the bump electrode is provided in a pluralit
6486493 Semiconductor integrated circuit device having hierarchical test interface circuit November 26, 2002
A plurality of test interface circuits are disposed in correspondence with a plurality of DRAM cores. An upper test interface circuit transmits a test control signal or the like supplied from the outside to each of or one of the plurality of test interface circuits in accordance with a
6483139 Semiconductor memory device formed on semiconductor substrate November 19, 2002
In a memory cell contained in a memory circuit portion of a system LSI, a gate electrode of an N-channel MOS transistor and a cell plate electrode of a capacitor are formed by the same interconnection layer. Thus, the system LSI can be produced using the CMOS logic process alone so that
6477108 Semiconductor device including memory with reduced current consumption November 5, 2002
When a row active command ACT_CMD is externally input, an internal clock control circuit activates a signal int.CKE, so that an external clock signal ext.CLK is responsively supplied to an internal memory array as signal int.CLK. Thus, clock control is meticulously conducted, whereby a
6456560 Semiconductor integrated circuit device with test interface circuit for performing test on embed September 24, 2002
A first test clock signal and a second test clock signal are generated from a common basic test clock signal using a delay line with a changeable delay time and a delay stage with a fixed delay time. A memory circuit is operated in synchronization with one of the first and second test cl
6452859 Dynamic semiconductor memory device superior in refresh characteristics September 17, 2002
A sense operation by a sense amplifier circuit is carried out by selecting a pair of subword lines simultaneously and coupling each bit line in a pair to a memory cell. Since complementary data are stored into these two memory cells, the voltage between the bit lines in a pair in a sense
6449204 DYNAMIC SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REARRANGING DATA STORAGE FROM A ONE BIT/ONE CELL September 10, 2002
In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected sta
6448602 Semiconductor memory device with improved arrangement of memory blocks and peripheral circuits September 10, 2002
A DRAM includes a semiconductor substrate and unit blocks. Each unit block includes a peripheral circuit and eight memory blocks arranged to surround the peripheral circuit. Each memory block includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a row
6442078 Semiconductor memory device having structure implementing high data transfer rate August 27, 2002
The inventive semiconductor memory device comprises an interface area transmitting/receiving data to/from an external device, an address-system circuit receiving an address signal from the interface area, a memory cell array (subarray), a preamplifier/write driver for writing data receiv
6418067 Semiconductor memory device suitable for merging with logic July 9, 2002
Read data line pairs, write data line pairs, a spare read data line pair, and a spare write data line pair are provided extending in the column direction over a memory cell array. Spare bit repair is performed by replacing a data line pair. Column redundancy control circuit changes the
6414890 Semiconductor memory device capable of reliably performing burn-in test at wafer level July 2, 2002
In a word line drive circuit for driving a word line to a boosted voltage level, a drive signal that is activated in response to a wafer burn-in signal is applied to the gate of a transistor for preventing the floating state of the word line. Even if a boost signal is transmitted to a
6414883 Semiconductor memory device July 2, 2002
Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The secon
6404684 Test interface circuit and semiconductor integrated circuit device including the same June 11, 2002
In a test interface circuit arranged between an embedded memory and a test data input/output (I/O) terminal, a first-in first-out circuit for successively storing test data is arranged for controlling a latency of data read from the embedded memory. The test interface circuit for the
6404056 Semiconductor integrated circuit June 11, 2002
On transistors P1, P2, N1 and N2 constituting an NAND gate, a interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interc
6400628 Semiconductor memory device June 4, 2002
A dummy bit line is formed from the same layer as and separately from a bit line, and is running in parallel with the bit line. Capacitor is formed on the layer upper than bit line and has a cell plate. An intermediate interconnection is formed on the layer upper than capacitor and is
6400625 Semiconductor integrated circuit device capable of performing operational test for contained mem June 4, 2002
A test interface circuit carries out an operational test based on a signal input to test pin terminals by directly accessing a DRAM core. A frequency multiplication circuit generates an internal test clock signal by multiplying the frequency of an external test clock signal input to the
6388929 Semiconductor memory device performing redundancy repair based on operation test and semiconduct May 14, 2002
A BIST circuit conducts an operation test on a memory cell array to detect a defective memory cell when power is turned on. On the basis of a result of the operation test, the BIST circuit generates a redundancy code indicative of a defect address corresponding to a defective memory cell
6388329 Semiconductor integrated circuit having three wiring layers May 14, 2002
A high melting point metal wiring layer, a second aluminum wiring layer, and a third aluminum wiring layer are stacked on transistors forming an inverter train of a hierarchical power supply structure respectively. The high melting point metal wiring layer is employed as a local wire for
6377508 Dynamic semiconductor memory device having excellent charge retention characteristics April 23, 2002
Level converter converts a word line group specifying signal, which is sent from a row decoder and has amplitude of a power supply potential Vcc and a ground potential GND, into mutually complementary logic signals WD and ZWD of a high voltage Vpp and a negative potential Vbb. An RX deco
6377483 Semiconductor memory device having improved memory cell and bit line pitch April 23, 2002
Tow bit lines are arranged in each column in which memory cells are disposed. For selecting a first group sub-word line, only a sense amplifier on one sense amplifier band is activated and for selecting a second group sub-word line, only a sense amplifier on the other sense amplifier
6373321 CMOS semiconductor device April 16, 2002
A semiconductor device includes a PMOS transistor and an NMOS transistor. In a standby state, a potential of Vcc level is applied to the substrate of the PMOS transistor and a potential of Vss level is applied to the substrate of the NMOS transistor. Therefore, the voltage between the
6341098 Semiconductor integrated circuit device having hierarchical power source arrangement January 22, 2002
A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period.
6337506 Semiconductor memory device capable of performing stable operation for noise while preventing in January 8, 2002
A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the
6333889 Logic-merged semiconductor memory having high internal data transfer rate December 25, 2001
Two memory sub arrays are provided adjacent to a read/write circuit. An internal data line pair corresponding to the memory sub array located farther away is connected to the read/write circuit via a feed-through line pair (FLP) located at an upper layer above the memory sub array lo
6304494 Semiconductor device with decreased power consumption October 16, 2001
A source potential control circuit applies supply potential V.sub.DD2 (<V.sub.DD1) to a common source line in a write operation and applies supply potential V.sub.DD1 thereto after data is inverted for restoring. Accordingly, supply potential can be reduced and thus reduced power
6272055 Semiconductor memory device August 7, 2001
Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The secon
6272034 Semiconductor memory device August 7, 2001
A control circuit portion which controls the operations of memory cells is concentrated in a central portion and heat radiation plates are placed thereon via adhesive. A semiconductor integrated circuit having a function of the MPU or the like is placed above the control circuit portion
6256252 Memory-embedded semiconductor integrated circuit device having low power consumption July 3, 2001
In a sleep mode, data held in a logic circuit is saved to a memory circuit under the control of a transfer control circuit, and thereafter supply of an operation power supply voltage to the logic circuit from a logic power source is stopped. A memory-embedded LSI capable of reducing curr
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