| Patent Number |
Title Of Patent |
Date Issued |
| 7617378 |
Multiprocessor system with retry-less TLBI protocol |
November 10, 2009 |
| A symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors to complete without causing delay. Each processor includes a TLBI register associated with the TLB and TLBI logic. The TLBI register |
| 7586936 |
Host Ethernet adapter for networking offload in server environment |
September 8, 2009 |
| An Ethernet adapter is disclosed. The Ethernet adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor. The plurality of layers include a demultiplexing mechanism to allow for partitioning of the processor. A Host Ether |
| 7526631 |
Data processing system with backplane and processor books configurable to support both technical |
April 28, 2009 |
| A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing systems with extern |
| 7502917 |
High speed memory cloning facility via a lockless multiprocessor mechanism |
March 10, 2009 |
| A processor chip that provides a dynamically selectable operating mode in which particular sequences of instructions are executed without an external interrupt. The processor chip comprises an architected bit that may be set by software and which enables the external interrupt of the |
| 7493478 |
Enhanced processor virtualization mechanism via saving and restoring soft processor/system state |
February 17, 2009 |
| A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Prefe |
| 7493446 |
System and method for completing full updates to entire cache lines stores with address-only bus |
February 17, 2009 |
| A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable |
| 7493417 |
Method and data processing system for microprocessor communication using a processor interconnec |
February 17, 2009 |
| Processor communication registers (PCRs) contained in each processor within a multiprocessor system and interconnected by a specialized bus provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel |
| 7475399 |
Method and data processing system optimizing performance through reporting of thread-level hardw |
January 6, 2009 |
| According to a method of operating a data processing system, one or more monitoring parameter sets are established in a processing unit within the data processing system. The processing unit monitors, in hardware, execution of each of a plurality of schedulable software entities within |
| 7448037 |
Method and data processing system having dynamic profile-directed feedback at runtime |
November 4, 2008 |
| Software communicates to a processing unit a classification each of at least one schedulable software entity that the processing unit executes. A resource manager within the processing unit dynamically allocates hardware resources within the processing unit to the schedulable software |
| 7360067 |
Method and data processing system for microprocessor communication in a cluster-based multi-proc |
April 15, 2008 |
| A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each process |
| 7360021 |
System and method for completing updates to entire cache lines with address-only bus operations |
April 15, 2008 |
| A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable |
| 7359932 |
Method and data processing system for microprocessor communication in a cluster-based multi-proc |
April 15, 2008 |
| A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector withi |
| 7356568 |
Method, processing unit and data processing system for microprocessor communication in a multi-p |
April 8, 2008 |
| A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has ex |
| 7308558 |
Multiprocessor data processing system having scalable data interconnect and data routing mechani |
December 11, 2007 |
| The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one application, a dat |
| 7308536 |
System bus read data transfers with data ordering control bits |
December 11, 2007 |
| A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the order in which to trans |
| 7272664 |
Cross partition sharing of state information |
September 18, 2007 |
| A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for the purpose of storing |
| 7213248 |
High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing |
May 1, 2007 |
| A multiprocessor data processing system includes a plurality of processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. A first processor executes a high speed instruction sequence including a load-type instruction to acquire |
| 7130967 |
Method and system for supplier-based memory speculation in a memory subsystem of a data processi |
October 31, 2006 |
| A data processing system includes one or more processing cores, a system memory having multiple rows of data storage, and a memory controller that controls access to the system memory and performs supplier-based memory speculation. The memory controller includes a memory speculation tabl |
| 7117388 |
Dynamic, Non-invasive detection of hot-pluggable problem components and re-active re-allocation |
October 3, 2006 |
| A method, system, and data processing system for dynamic detection of problem components in a hot-plug processing system and automatic removal of the problem component via hot-removal methods without disrupting processing of the overall system. A data processing system that provides |
| 7117319 |
Managing processor architected state upon an interrupt |
October 3, 2006 |
| A method and system are disclosed for managing a hard architected state of a processor that is critical for executing a process in the processor. A shadow copy of the hard architected state is stored from the processor to memory when an interrupt is received by the processor. The shadow |
| 7117126 |
Data processing system and method with dynamic idle for tunable interface calibration |
October 3, 2006 |
| A data processing system includes a mechanism to periodically idle the normal system operation to allow recalibration of its interface circuitry by transmission of data with transitions and logic levels indicative of actual operation. Provision is made to protect actual data of the syste |
| 7089364 |
System and method to stall dispatch of gathered store operations in a store queue using a timer |
August 8, 2006 |
| A method and processor system that substantially enhances the store gathering capabilities of a store queue entry to enable gathering of a maximum number of proximate-in-time store operations before the entry is selected for dispatch. A counter is provided for each entry to track a t |
| 7073043 |
Multiprocessor system supporting multiple outstanding TLBI operations per partition |
July 4, 2006 |
| Disclosed is a symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors within a partition to complete concurrently. Thus, a global TLB lock, synchronization, and TLB unlock is not necessary. Wh |
| 7073004 |
Method and data processing system for microprocessor communication in a cluster-based multi-proc |
July 4, 2006 |
| The address tenure for PCR synchronization operations is redefined to support inclusion of the synchronization data within the address tenure. The bits of a particular field within the address tenure (e.g., the address field) are re-allocated to synchronization data, which is known t |
| 7069394 |
Dynamic data routing mechanism for a high speed memory cloner |
June 27, 2006 |
| A method for enabling concurrent, overlapping data moves associated with separate data clone operations of different memory cloners. A first data is being moved from its source to a destination. The first data is tagged with the address of the first destination to identify the data, and |
| 7047320 |
Data processing system providing hardware acceleration of input/output (I/O) communication |
May 16, 2006 |
| An integrated circuit, such as a processing unit, includes a substrate and integrated circuitry formed in the substrate. The integrated circuitry includes a processor core that executes instructions, an interconnect interface, coupled to the processor core, that supports communication |
| 7039832 |
Robust system reliability via systolic manufacturing level chip test operating real time on micr |
May 2, 2006 |
| A method and system are disclosed for running a manufacturing-level test program on an installed processor by interrupting processor execution of a non-test process. Periodic execution of the manufacturing-level test program allows the processor to continually self-test during normal |
| 7039760 |
Programming means for dynamic specifications of cache management preferences |
May 2, 2006 |
| A method and apparatus for managing cache lines in a data processing system. A special purpose register is employed in which this register may be manipulated by user code and operating system code to set preferences, such as a level 2 cache management policy preference for an application |
| 7017031 |
Method, apparatus and system for managing released promotion bits |
March 21, 2006 |
| A data processing system includes a global promotion facility containing a plurality of promotion bit fields, an interconnect, and a plurality of processing units coupled to the global promotion facility and to the interconnect. A first processing unit includes an instruction sequencing |
| 7017024 |
Data processing system having no system memory |
March 21, 2006 |
| A data processing system having no system memory is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the |
| 7007128 |
Multiprocessor data processing system having a data routing mechanism regulated through control |
February 28, 2006 |
| A data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one implementation, a da |
| 6996693 |
High speed memory cloning facility via a source/destination switching mechanism |
February 7, 2006 |
| Disclosed is a data processing system that completes a data clone operation by routing the directly from a source location within said memory subsystem to a destination location within said memory subsystem. The data is not routed through the processor that initiated the data clone o |
| 6990545 |
Non-disruptive, dynamic hot-plug and hot-remove of server nodes in an SMP |
January 24, 2006 |
| A data processing system that provides hot-plug add and remove functionality for individual, hot-pluggable components without disrupting current operations of the overall processing system. The processing system includes an interconnect fabric that includes hot plug connector at whic |
| 6986013 |
Imprecise cache line protection mechanism during a memory clone operation |
January 10, 2006 |
| A method for avoiding livelock within a multiprocessor data processing system when there are multiple, concurrent clone operations to similar memory data locations within a data processing system. A set of tokens are defined within the memory cloner for use prior to conducting a clone |
| 6986011 |
High speed memory cloner within a data processing system |
January 10, 2006 |
| A processor chip with a high speed memory cloner that enables movement of data directly from one memory location (of a data processing system) to another without the data having to be routed through the processor. The memory cloner includes processing logic that enables the release of th |
| 6983347 |
Dynamically managing saved processor soft states |
January 3, 2006 |
| A method and system are disclosed for managing stored soft state information, such as the contents of cache memory and address translation information that are non-critical for executing a process within a processor. The soft states of idle processes are stored in system memory in vi |
| 6981083 |
Processor virtualization mechanism via an enhanced restoration of hard architected states |
December 27, 2005 |
| A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next proces |
| 6976148 |
Acceleration of input/output (I/O) communication through improved address translation |
December 13, 2005 |
| An I/O communication adapter receives from a processor core an I/O command referencing an effective address within an effective address space of the processor core that identifies a storage location. In response to receipt of the I/O command, the I/O communication adapter translates the |
| 6970976 |
Layered local cache with lower level cache optimizing allocation mechanism |
November 29, 2005 |
| A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning t |
| 6963967 |
System and method for enabling weak consistent storage advantage to a firmly consistent storage |
November 8, 2005 |
| Disclosed is a method of processing instructions in a data processing system. An instruction sequence that includes a memory access instruction is received at a processor in program order. In response to receipt of the memory access instruction a memory access request and a barrier opera |
| 6944721 |
Asynchronous non-blocking snoop invalidation |
September 13, 2005 |
| A method and system for avoiding live locks caused by repeated retry responses sent from a first cache memory that is in the process of manipulating a cache line that a second cache memory is attempting invalidate in the first cache memory. To a live lock condition caused by multiple |
| 6928524 |
Data processing system with naked cache line write operations |
August 9, 2005 |
| A method for reserving memory buffers for receiving data prior to the actual movement of data on a data processing system. A naked write operation is generated that includes a destination address and an address of the processor generating the write operation. The naked write operation |
| 6925551 |
Method, apparatus and system for accessing a global promotion facility through execution of a br |
August 2, 2005 |
| A multiprocessor data processing system includes first and second processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. The first processor initiates execution of a branch-type instruction to request acquisition of a pro |
| 6920521 |
Method and system of managing virtualized physical memory in a data processing system |
July 19, 2005 |
| A move engine and operating system transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. The operating system stores FROM and TO real addresses in unique fields in memory that are used to virtualize the physical address of the |
| 6920514 |
Method, apparatus and system that cache promotion information within a processor separate from i |
July 19, 2005 |
| A data processing system includes a global promotion facility and a plurality of processing units coupled by an interconnect. At least one processing unit among the plurality of processing units includes one or more second caches having cache arrays in which instructions and operand |
| 6915390 |
High speed memory cloning facility via a coherently done mechanism |
July 5, 2005 |
| A processing state that enables a processor to resume processing operations before completion of a processor-issued data move operation. The processor executes instructions specifying a data clone operation and delays subsequent instruction execution while waiting for a receipt of an |
| 6910062 |
Method and apparatus for transmitting packets within a symmetric multiprocessor system |
June 21, 2005 |
| The symmetric multiprocessor system includes multiple processing nodes, with multiple agents at each node, connected to each other via an interconnect. A request transaction is initiated by a master agent in a master node to all receiving nodes. A write counter number is generated fo |
| 6907494 |
Method and system of managing virtualized physical memory in a memory controller and processor s |
June 14, 2005 |
| A processor contains a move engine and a memory controller contains a mapping engine that, together, transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores current and new real addresses that enab |
| 6904490 |
Method and system of managing virtualized physical memory in a multi-processor system |
June 7, 2005 |
| A processor contains a move engine and mapping engine that transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores FROM and TO real addresses that enable the engines to virtualize the physical |
| 6901485 |
Memory directory management in a multi-node computer system |
May 31, 2005 |
| A computer system includes a home node and one or more remote nodes coupled by a node interconnect. The home node includes a local interconnect, a node controller coupled between the local interconnect and the node interconnect, a home system memory, a memory directory including a pl |
