| Patent Number |
Title Of Patent |
Date Issued |
| 7603672 |
Programmable request handling system and method |
October 13, 2009 |
| A system and method is disclosed for prioritizing requests received from multiple requesters for presentation to a shared resource. The system includes logic that implements multiple priority schemes. This logic may be programmably configured to associate each of the requesters with any |
| 7356647 |
Cache with integrated capability to write out entire cache |
April 8, 2008 |
| A cache arrangement of a data processing system provides a cache flush operation initiated by a command from a maintenance processor. The cache arrangement includes a cache memory, a mode register, and a controller. The mode register is settable by the maintenance processor to one of |
| 6993630 |
Data pre-fetch system and method for a cache memory |
January 31, 2006 |
| A system and method for pre-fetching data signals is disclosed. According to one aspect of the invention, an Instruction Processor (IP) generates requests to access data signals within the cache. Predetermined ones of the requests are provided to pre-fetch control logic, which determines |
| 6976128 |
Cache flush system and method |
December 13, 2005 |
| A system and method is provided to selectively flush data from cache memory to a main memory irrespective of the replacement algorithm that is used to manage the cache data. According to one aspect of the invention, novel "page flush" and "cache line flush" instructions are provided to f |
| 6973541 |
System and method for initializing memory within a data processing system |
December 6, 2005 |
| An improved system and method are provided for initializing memory in a data processing system. According to one aspect of the invention, a "page zero" instruction is provided that may be executed by an Instruction Processor to initiate memory initialization. Upon instruction execution, |
| 6934810 |
Delayed leaky write system and method for a cache memory |
August 23, 2005 |
| A mechanism to selectively leak data signals from a cache memory is provided. According to one aspect of the invention, an Instruction Processor (IP) is coupled to generate requests to access data signals within the cache. Some requests include a leaky designator, which is activated |
