| Patent Number |
Title Of Patent |
Date Issued |
| 7613898 |
Virtualizing an IOMMU |
November 3, 2009 |
| In one embodiment, a system comprises one or more input/output (I/O) devices; an I/O memory management unit (IOMMU) coupled to receive memory requests sourced by the I/O devices and configured to provide address translation for the memory requests; and a virtual machine monitor (VMM) |
| 7606985 |
Augmented instruction set for proactive synchronization within a computer system |
October 20, 2009 |
| Providing proactive synchronization in a computer system may include providing an augmented instruction set with additional synchronizing instructions. Therefore, a method includes a processor executing a set of instructions to request exclusive access to a plurality of memory resour |
| 7555633 |
Instruction cache prefetch based on trace cache eviction |
June 30, 2009 |
| Various embodiments of methods and systems for implementing a microprocessor that fetches a group of instructions into instruction cache in response to a corresponding trace being evicted from the trace cache are disclosed. In some embodiments, a microprocessor may include an instruc |
| 7552290 |
Method for maintaining atomicity of instruction sequence to access a number of cache lines durin |
June 23, 2009 |
| A method for maintaining atomicity of a sequence of instructions includes a processor requesting exclusive access to a given memory resource. The request may include executing a critical section of code having memory reference instructions each including a LOCK prefix, and the memory |
| 7548999 |
Chained hybrid input/output memory management unit |
June 16, 2009 |
| In one embodiment, an input/output (I/O) node comprises an I/O memory management unit (IOMMU) configured to translate memory requests. The I/O node is configured to couple to an interconnect and to operate as a tunnel on the interconnect, and wherein the IOMMU is configured translate |
| 7543131 |
Controlling an I/O MMU |
June 2, 2009 |
| In an embodiment, a computer system comprises a processor; a memory management module comprising a plurality of instructions executable on the processor; a memory coupled to the processor; and an input/output memory management unit (IOMMU) coupled to the memory. The IOMMU is configur |
| 7516247 |
Avoiding silent data corruption and data leakage in a virtual environment with multiple guests |
April 7, 2009 |
| In an embodiment, an input/output memory management unit (IOMMU) is configured to receive a completion wait command defined to ensure that one or more preceding invalidation commands are completed by the IOMMU prior to a completion of the completion wait command. The IOMMU is configu |
| 7480784 |
Ensuring deadlock free operation for peer to peer traffic in an input/output memory management u |
January 20, 2009 |
| In one embodiment, an input/output memory management unit (IOMMU) comprises a cache to cache translation data from memory; and a control unit coupled to the cache. The control unit is configured to implement address translation and memory protection for memory requests sourced by one |
| 7315935 |
Apparatus and method for port arbitration in a register file on the basis of functional unit iss |
January 1, 2008 |
| A microprocessor is configured to provide port arbitration in a register file. The microprocessor includes a plurality of functional units configured to collectively operate on a maximum number of operands in a given execution cycle, and a register file providing a number of read por |
| 7263600 |
System and method for validating a memory file that links speculative results of load operations |
August 28, 2007 |
| A system and method for linking speculative results of load operations to register values. A system includes a memory file including an entry configured to store a first addressing pattern and a first tag. The memory file is configured to compare the first addressing pattern to a sec |
| 7251710 |
Cache memory subsystem including a fixed latency R/W pipeline |
July 31, 2007 |
| A cache memory subsystem including a fixed latency read/write pipeline. The cache memory subsystem includes a cache storage which may be configured to store a plurality of cache lines of data. The cache memory subsystem further includes a scheduler which may be configured to schedule |
| 7197630 |
Method and system for changing the executable status of an operation following a branch mispredi |
March 27, 2007 |
| A method and system for changing the executable status of an operation following a branch misprediction. In one embodiment, a method may include predicting an execution path of a first conditional branch operation stored in an entry of a trace cache, and in response to predicting the |
| 7133975 |
Cache memory system including a cache memory employing a tag including associated touch bits |
November 7, 2006 |
| A cache memory system including a cache memory employing a tag including associated touch bits. The system includes a first cache memory subsystem having a first cache storage and a second cache memory subsystem including a second cache storage. The first cache storage may store a fi |
| 7133969 |
System and method for handling exceptional instructions in a trace cache based processor |
November 7, 2006 |
| A system may include an instruction cache, a trace cache including a plurality of trace cache entries, and a trace generator coupled to the instruction cache and the trace cache. The trace generator may be configured to receive a group of instructions output by the instruction cache |
| 7124236 |
Microprocessor including bank-pipelined cache with asynchronous data blocks |
October 17, 2006 |
| A microprocessor including a level two cache memory including asynchronously accessible cache blocks. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a plurality of storage blocks, each configured to store a plurality of data units. Ea |
| 7073026 |
Microprocessor including cache memory supporting multiple accesses per cycle |
July 4, 2006 |
| A microprocessor including a level two cache memory which supports multiple accesses per cycle. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a cache memory coupled to a plurality of buses. The cache memory includes a plurality of in |
| 7069411 |
Mapper circuit with backup capability |
June 27, 2006 |
| A mapper circuit with backup capability. In one embodiment, the mapper circuit may store associations between physical register names (PRNs) and logical register names (LRNs) in a plurality of storage locations, each of the storage locations corresponding to a speculative state. One of t |
| 7043626 |
Retaining flag value associated with dead result data in freed rename physical register with an |
May 9, 2006 |
| A method and apparatus for retaining flag values when an associated data value dies. A first storage circuit includes a free list for storing physical register names (PRNs) and indications indicative of whether a physical register associated with a PRN was assigned to store a logical |
| 7003629 |
System and method of identifying liveness groups within traces stored in a trace cache |
February 21, 2006 |
| A microprocessor may include a trace cache and a trace generator. The trace cache includes several trace cache entries. Each trace cache entry is configured to store several operations and a respective set of liveness indications. The operations are generated by at least partially de |
| 6976147 |
Stride-based prefetch mechanism using a prediction confidence value |
December 13, 2005 |
| A prefetch mechanism includes a prefetch predictor table coupled to a prefetch control. The prefetch predictor table may include a plurality of locations configured to store a plurality of entries each indicative of a stride between a respective pair of memory requests. Each of the plura |
| 6950925 |
Scheduler for use in a microprocessor that supports data-speculative execution |
September 27, 2005 |
| A microprocessor may include several execution units and a scheduler coupled to issue operations to at least one of the execution units. The scheduler may include several entries. A first entry may be allocated to a first operation. The first entry includes a source status indication for |
| 5694564 |
Data processing system a method for performing register renaming having back-up capability |
December 2, 1997 |
| In a data processing system, a method for performing register renaming with back-up capability. A register renaming apparatus (18) comprises a logical-physical (LP) register map (30), a free list (32), and an internal swap bus (90) for exchanging information between the two. The register |
